A semiconductor device includes first, second and third stacked chips with a first, second and third substrate, respectively, at least three first, second and third logical circuits, respectively, and at least two first, second and third vias, respectively, and a fourth chip stacked on the third chip having a fourth substrate, and at least three fourth logical circuits. First and second ones of the first to third logical circuits of the first to fourth chips are each configured to perform a first and second logical operation, respectively, on a first and second address input signal, respectively, received at the respective chip to thereby output a first and second address output signal, respectively. Third ones are each configured to activate the respective chip based on at least the second address output signal transmitted within the respective chip.

A method of manufacturing a semiconductor package may include: preparing a semiconductor wafer including rear pads and a rear insulating layer surrounding the rear pads, the rear insulating layer including first recesses spaced apart from the rear pads in a first lateral direction; preparing second semiconductor chips including front pads and a front insulating layer surrounding the front pads, the front insulating layer including second recesses spaced apart from the front pads in the first lateral direction; forming an air gap between the first recesses and the second recesses in a vertical direction by disposing the second semiconductor chips on the semiconductor wafer, the rear pads contacting the front pads; and bonding the rear insulating layer and the front insulating layer to each other and bonding the rear pads and the front pads to each other by performing a thermal compression process.

A light-emitting device includes a substrate and an epitaxial unit. The substrate has a first and a second surface. The substrate is formed on the first surface with a plurality of protrusions. The epitaxial unit includes a first semiconductor layer, an active layer, and a second semiconductor layer that are sequentially disposed on the first surface of the substrate. The first surface of the substrate has a first area that is not covered by the epitaxial unit, and a second area this is covered by the epitaxial unit. A height difference (h2) between the first area and the second area is no greater than 1 m. A display apparatus and a lighting apparatus are also disclosed.

A display panel comprising a display substrate having a display area and a pad area disposed around the display area. A connection wire is disposed on the pad area of the display substrate. A signal wire is disposed on the connection wire. A supporter is disposed between the display substrate and the connection wire. The connection wire directly contacts the supporter.

A semiconductor device includes: a lower semiconductor structure including a plurality of first lower electrode bonding pads, a plurality of second lower electrode bonding pads, and a lower connection pattern connecting the plurality of first lower electrode bonding pads to each other while being connected to a first voltage; and an upper semiconductor structure disposed over the lower semiconductor structure and including a plurality of first upper electrode bonding pads, a plurality of second upper electrode bonding pads, and an upper connection pattern connecting the plurality of second upper electrode bonding pads to each other while being connected to a second voltage different from the first voltage, wherein the plurality of first lower electrode bonding pads are bonded to the plurality of first upper electrode bonding pads, respectively, and the plurality of second lower electrode bonding pads are bonded to the plurality of second upper electrode bonding pads, respectively.

A semiconductor device includes: a lower semiconductor structure including one or more first lower test pads, one or more second lower test pads that are alternately arranged with the one or more first lower test pads, and a lower test terminal that is electrically connected to the second lower test pad through a second lower test line; and an upper semiconductor structure positioned over the lower semiconductor structure and including an upper test pad and an upper test terminal that is electrically connected to the upper test pad through an upper test line, wherein, when the lower semiconductor structure and the upper semiconductor structure are aligned, the upper test pad overlaps with and contacts a corresponding first lower test pad among the one or more first lower test pads, and is spaced apart from the second lower test pad that is adjacent to the corresponding first lower test pad.

A semiconductor chip may include: a semiconductor substrate; a through silicon via that vertically penetrates the semiconductor substrate; an integrated device layer on a first surface of the semiconductor substrate and including integrated devices; a multi-wiring layer on the integrated device layer and including layers of wires; an upper metal layer on the multi-wiring layer and connected to the wires; and a lower metal layer on a second surface of the semiconductor substrate. The semiconductor substrate may include a lower bump area on the second surface of the semiconductor substrate, the lower bump area including bump pads thereon, and the lower metal layer may be on a periphery of the lower bump area.

A chip includes a semiconductor substrate, integrated circuits with at least portions in the semiconductor substrate, and a surface dielectric layer over the integrated circuits. A plurality of metal pads is distributed substantially uniformly throughout substantially an entirety of a surface of the chip. The plurality of metal pads has top surfaces level with a top surface of the surface dielectric layer. The plurality of metal pads includes active metal pads and dummy metal pads. The active metal pads are electrically coupled to the integrated circuits. The dummy metal pads are electrically decoupled from the integrated circuits.

A semiconductor device, including: a semiconductor chip having an element forming surface; an insulating layer formed on the element forming surface of the semiconductor chip; a barrier conductive layer formed on the insulating layer; a pad wiring layer including a plurality of conductive layers, one of the plurality of conductive layers including an eaves portion protruding to an outward direction; a bonding member that is bonded to the pad wiring layer and supplies electric power to an element of the element forming surface; and a coating insulating film that is selectively formed on the insulating layer below the eaves portion, exposes an upper surface of the insulating layer to a peripheral region of the pad wiring layer, and coats both an upper surface and a side surface of an end portion of the barrier conductive layer.

A power chip packaging structure includes: a ceramic substrate; a first and a second top metal layers are formed on the ceramic substrate; a bottom metal layer formed on the ceramic substrate; a power chip having an active surface and a chip back surface. The active surface has a contact pad, and the chip back surface is connected to the first top metal layer. One or more first copper layers are formed on the contact pad, a top surface of the first copper layer has a peripheral region and an arrangement region surrounded by the peripheral region. Multiple second copper layers are formed in the arrangement region and separated from each other. Each of multiple wires is respectively connected to the second copper layer with one end and connected to the second top metal layer with the other end.