A semiconductor device includes a first stacked body and a second stacked body bonded to the first stacked body. The first stacked body includes a first pad provided on a first bonding surface to which the first stacked body and the second stacked body are bonded. The second stacked body includes a second pad bonded to the first pad on the first bonding surface. When a direction from the first stacked body to the second stacked body is defined as a first direction, a direction intersecting with the first direction is defined as a second direction, a direction intersecting with the first direction and the second direction is defined as a third direction, dimensions of the first pad and the second pad in the third direction are defined as PX1 and PX2, respectively, and dimensions of the first pad and the second pad in the second direction are defined as PY1 and PY2, respectively, the dimensions of the first pad and the second pad satisfy at least one of Equations (1) and (2) below.

[00001]$\begin{array}{cc}\mathrm{PX}1>\mathrm{PY}1& \left(1\right)\end{array}$$\begin{array}{cc}\mathrm{PY}2>\mathrm{PX}2& \left(2\right)\end{array}$

A chip includes a semiconductor substrate, integrated circuits with at least portions in the semiconductor substrate, and a surface dielectric layer over the integrated circuits. A plurality of metal pads is distributed substantially uniformly throughout substantially an entirety of a surface of the chip. The plurality of metal pads has top surfaces level with a top surface of the surface dielectric layer. The plurality of metal pads includes active metal pads and dummy metal pads. The active metal pads are electrically coupled to the integrated circuits. The dummy metal pads are electrically decoupled from the integrated circuits.

Representative techniques and devices including process steps may be employed to mitigate the potential for delamination of bonded microelectronic substrates due to metal expansion at a bonding interface. For example, a metal pad having a larger diameter or surface area (e.g., oversized for the application) may be used when a contact pad is positioned over a TSV in one or both substrates.

A semiconductor storage device includes first and second chips. The second chip has a memory region and an edge seal region, and includes a plurality of edge seals, a first wiring layer at a first layer level on a first chip side of the edge seals, and a second wiring layer at a second layer level and contains tungsten. The first wiring layer includes first wirings at positions overlapping with inner edge seals, respectively, but not with an outermost edge seal and electrically connected to the inner edge seals, respectively. The second wiring layer includes second wirings that are provided at positions overlapping with the inner edge seals, respectively, but not with the outermost edge seal, and electrically connected to the inner edge seals, respectively, and a third wiring provided on an outer side of the second wirings, and electrically separated and spaced apart from the outermost edge seal.

A light emitting device including a substrate having a protruding pattern on an upper surface thereof, a first sub-unit disposed on the substrate, a second sub-unit disposed between the substrate and the first sub-unit, a third sub-unit disposed between the substrate and the second sub-unit, a first insulation layer at least partially in contact with side surfaces of the first, second, and third sub-units, and a second insulation layer at least partially overlapping with the first insulation layer, in which at least one of the first insulation layer and the second insulation layer includes a distributed Bragg reflector.

The present application provides a semiconductor structure having a dummy conductive member, and a manufacturing method of the semiconductor structure. The semiconductor structure includes a first wafer including a first substrate, a first dielectric layer over the first substrate, a first bonding layer over the first dielectric layer, a first via extending through the first bonding layer, and a first dummy conductive member disposed adjacent to the first via and extending partially through the first bonding layer; and a second wafer including a second bonding layer over the first bonding layer, a second via extending through the second bonding layer, a second dummy conductive member disposed adjacent to the second via and extending partially through the second bonding layer, a second dielectric layer over the second bonding layer, and a second substrate over the second dielectric layer.

A semiconductor package including a package substrate, a plurality of upper substrate pads, an image sensor chip on the package substrate, where the image sensor chip includes a sensing region and a pad region at least partially surrounding the sensing region, a plurality of chip pads and a plurality of dummy pads in the pad region, a plurality of bonding wires each electrically connecting respective ones of the plurality of upper substrate pads of the package substrate to respective ones of the plurality of chip pads, a reinforcement wire structure including a plurality of reinforcement wires each connecting at least two dummy pads of the plurality of dummy pads, a dam structure on the plurality of dummy pads and the reinforcement wire structure, a glass on the dam structure and the image sensor chip, and a molding member on the image sensor chip and the plurality of bonding wires.

A method includes depositing a first dielectric layer on a first substrate of a first device die, etching the first dielectric layer to form a trench, depositing a metallic material in the trench and on a top surface of the first dielectric layer, and performing a chemical mechanical polish (CMP) process to remove a portion of the metallic material from the top surface of the first dielectric layer to form a first metal pad. After the performing of the CMP process, the method selectively etches the first metal pad to form recesses at an edge portion of the first metal pad, deposits a second dielectric layer on a second substrate of a second device die, forms a second metal pad in the second dielectric layer, and bonds the second device die to the first device die.

A semiconductor device may include a first substrate including device and edge regions, a first insulating structure on the first substrate, first metal pads and first dummy pads at the uppermost end of the first insulating structure, a second insulating structure on the first insulating structure, second metal pads and second dummy pads at the lowermost end of the second insulating structure, a first interconnection structure in the first insulating structure, electrically connected to the first metal pads and electrically isolated from the first dummy pads, and a second interconnection structure in the second insulating structure, electrically connected to the second metal pads, and electrically isolated from the second dummy pads. Ones of the first metal pads may be in contact with respective ones of the second metal pads on the device region, and ones of the first dummy pads may be in contact with respective ones of the second dummy pads on the edge region.

The present disclosure relates to semiconductor devices, and semiconductor devices according to example embodiments include a first substrate structure and a second substrate structure on the first substrate structure, the first substrate structure including a first substrate including a cell area and a scribe lane area surrounding the cell area, first bonding pads over the cell area of the first substrate, and first dummy pads on the first substrate in the scribe lane area, the second substrate structure including a second substrate on the first substrate, and second bonding pads between the first substrate and the second substrate, joined with the plurality of first bonding pads, and a sum of the areas of the first dummy pads per a unit area in the scribe lane area is greater than or equal to a sum of the areas of the first bonding pads per a unit area in the cell area.