A semiconductor device includes a first die pad, a first semiconductor element, a second die pad, a second semiconductor element, a sealing resin, a first lead, a second lead, a third lead, and a fourth lead. The first lead, the second lead, the third lead, and the fourth lead are each spaced apart from the third side and the fourth side of the sealing resin and are exposed externally from either the first side surface or the second side surface of the sealing resin. Viewed in a third direction perpendicular to the first direction and the second directions, an area of the first die pad is larger than an area of the second die pad. Viewed in the third direction, each of the first lead and the third lead is separated away in the first direction from a first virtual line toward a side where the first side surface of the sealing resin is located.

A semiconductor and a method of fabricating the semiconductor having multiple, interconnected die including: providing a semiconductor substrate having a plurality of disparate die formed within the semiconductor substrate, and a plurality of scribe lines formed between pairs of adjacent die of the plurality of disparate die; and fabricating, by a lithography system, a plurality of inter-die connections that extend between adjacent pair of die of the plurality of die.

A solid state circuit breaker structure and electronic switching circuit is provided. The solid state circuit breaker structure includes a power substrate, a power die, a plurality of bond wires, and a magnetic body. The power die is mounted on the power substrate. The bond wires extend outwardly from the power die. The magnetic body is attached to the power substrate and disposed to increase a magnetic field produced by a current flowing through the bond wires and thereby produce a first inductance that produces a decrease in an overvoltage at turn off of the power die.

Semiconductor device packages including leads for enhanced video bandwidth and related operating criteria are described. An example package includes a flange having a top surface, a frame secured to the flange, and a pair of output leads. The frame forms an air cavity bounded in part by the top surface of the flange. The pair of output leads extend from outside the frame, through at least a portion of the frame, and to within the air cavity. The package also includes a decoupling lead positioned between the pair of output leads. The package also includes a second decoupling lead positioned between the pair of output leads in some examples. The decoupling lead or leads between the output leads facilitate the use of off-package decoupling capacitors to meet video bandwidth and other operating specifications. The package can also include one or more additional decoupling leads between input leads.

A semiconductor arrangement includes first and second controllable semiconductor devices forming a half-bridge arrangement, each controllable semiconductor device including a control electrode and a controllable load path between a first load electrode and a second load electrode. At least one gate driver is configured to generate one or more control signals for one or more of the controllable semiconductor devices. The first controllable semiconductor device is arranged on and electrically coupled to a first lead frame of a plurality of lead frames. The second controllable semiconductor device is arranged on and electrically coupled to a second lead frame of the plurality of lead frames. The controllable semiconductor devices and the at least one gate driver are arranged in a molded package. Each lead frames is partly covered by the molded package and has at least one surface or section that is not covered by the molded package.

A semiconductor device including a capacitive HV isolation component and a method of fabrication thereof is disclosed. In one example, the semiconductor device comprises a semiconductor substrate, a bottom capacitor plate over the semiconductor substrate, a top capacitor plate over the bottom capacitor plate, and one or more conductive posts extending between the bottom plate and the top plate.

A semiconductor package includes a package substrate, a processor chip mounted on a first region of the package substrate, a plurality of memory chips mounted on a second region of the package substrate being spaced apart from the first region of the package substrate, a signal transmission device mounted on a third region of the package substrate between the first and second regions of the package substrate, and a plurality of first bonding wires connecting the plurality of memory chips to the signal transmission device. The signal transmission device includes upper pads connected to the plurality of first bonding wires, penetrating electrodes arranged in a main body portion of the signal transmission device and connected to the upper pads, and lower pads in a lower surface portion of the signal transmission device and connected to the penetrating electrodes and connected to the package substrate via bonding balls.

A semiconductor device includes: an insulated circuit substrate including a base plate, a resin layer on the base plate, and a circuit pattern on the resin layer; a semiconductor chip that is rectangular and is bonded to the circuit pattern such that a side edge of the semiconductor chip is spaced inwardly from an outer peripheral edge of the circuit pattern by a predetermined distance; a case on the resin layer and surrounds the circuit pattern and the semiconductor chip; and a sealing material that covers the insulated circuit substrate and semiconductor chip and is surrounded by the case. The predetermined distance and thickness of the circuit pattern are greater than or equal to 0.1 of a length of one side of the semiconductor chip. A peripheral region of the case and a peripheral region of the resin layer are connected to each other via an adhesive layer.

A semiconductor component has a circuit carrier with a first conductor layer, in which a first conductor path is formed. A first thyristor chip has, on its upper face, an anode contact and a gate contact and, on its lower face, a cathode contact placed for electrical connection on the first conductor path. A second thyristor chip has, on its upper face, a cathode contact and a gate contact and, on its lower face, an anode contact placed for electrical connection on the first conductor path. At least one electrically conductive connection element connects the anode contact of the first thyristor chip to the cathode contact of the second thyristor chip. The first conductor path thus establishes an electrical connection between the cathode contact of the first thyristor chip and the anode contact of the second thyristor chip.

An electronic device includes: an insulating substrate including an obverse surface facing a thickness direction; a wiring portion formed on the substrate obverse surface and made of a conductive material; a lead frame arranged on the substrate obverse surface; a first and a second semiconductor elements electrically connected to the lead frame; and a first control unit electrically connected to the wiring portion to operate the first semiconductor element as a first upper arm and operate the second semiconductor element as a first lower arm. The lead frame includes a first pad portion to which the first semiconductor element is joined and a second pad portion to which the second semiconductor element is joined. The first and second pad portions are spaced apart from the wiring portion and arranged in a first direction with a first separation region sandwiched therebetween, where the first direction is orthogonal to the thickness direction. The first control unit is spaced apart from the lead frame as viewed in the thickness direction, while overlapping with the first separation region as viewed in a second direction orthogonal to the thickness direction and the first direction.