A semiconductor module arrangement includes a first substrate having a dielectric insulation layer and a first metallization layer arranged on a surface of the dielectric insulation layer. The first metallization layer includes first, second, third, and fourth sections. The semiconductor module arrangement further includes two or more controllable semiconductor elements each including first, second, and third contact pads. The second contact pad of each controllable semiconductor element is electrically coupled to the first section. The first contact pad of each controllable semiconductor element is electrically coupled to the second section by one or more electrical connection elements. The third contact pad of each controllable semiconductor element is electrically coupled to the third section by one or more electrical connection elements. The first contact pad of each controllable semiconductor element is electrically coupled to the fourth section by one or more electrical connection elements.

A microelectronic device package includes: a package substrate having a first set of leads spaced from a first die pad configured for mounting semiconductor devices, and a second set of leads spaced from a second die pad configured for mounting additional semiconductor devices, the first die pad and the first set of leads spaced from the second die pad and the second set of leads. Semiconductor devices are mounted to the first die pad and second die pad. A ceramic interposer is mounted to the package substrate in thermal contact with at least the first die pad. Mold compound covers the semiconductor devices, a portion of the ceramic interposer, and portions of the first set and the second set of leads.

According to one embodiment, a semiconductor device includes a first transistor and a second transistor whose source electrodes are electrically coupled to each other; a light emitter; a light receiver including a first cathode electrode and a second cathode electrode and configured to turn the first transistor and the second transistor on or off, depending on a light emission state of the light emitter; a first filter electrically coupling the first cathode electrode of the light receiver and the source electrode of the first transistor; and a second filter electrically coupling the second cathode electrode of the light receiver and the source electrode of the second transistor.

In examples, a semiconductor package comprises a semiconductor die having a device side including circuitry and a non-device side opposing the device side. The semiconductor package comprises a polyimide substrate coupled to the non-device side of the semiconductor die by an adhesive layer. The semiconductor package comprises a conductive terminal coupled to the polyimide substrate by the adhesive layer, and a bond wire coupled to the device side of the semiconductor die and to the conductive terminal. The semiconductor package comprises a mold compound covering the semiconductor die, the polyimide substrate, the bond wire, and at least part of the conductive terminal, with the conductive terminal extending to an exterior of the mold compound.

A semiconductor device includes: a second metal pattern electrically connected to a first semiconductor element and a second semiconductor element; a third metal pattern electrically connected to the second semiconductor element; a fifth metal pattern electrically connected to the third semiconductor element and a fourth semiconductor element; a sixth metal pattern electrically connected to the fourth semiconductor element; and a first conductive portion straddling the third metal pattern and the sixth metal pattern in plan view and electrically connecting the second metal pattern and the fifth metal pattern.

Examples of low capacitance bidirectional and unidirectional electrostatic discharge (ESD) protection devices for high voltage (e.g., 15 kV, 30 kV) applications are provided. Such devices include a circuit of a diode and a Zener diode coupled via their anodes to form an NPN structure and another, low capacitance diode coupled in series with the NPN structure. Such circuit may be configured on each of two dies, and the circuits coupled via wire bonds. Additional wire bonds may be used to respectively couple two pins of the device to the two circuits, or the pins may be coupled to the circuits via respective conductive die attaches. In a multichip module (MCM) topology, the NPN diode structure may be coupled to two low capacitance diodes on one die, and that circuit may be coupled to a third low capacitance diode disposed on another die. Some arrangements employ an insulator in conjunction with a single die. Some arrangements enable FlipChip fabrication technology.

An isolated power chip based on wafer level packaging, including: an RDL-based micro-transformer, where a primary coil of the RDL-based micro-transformer is connected to a direct-current power supply and configured to output a direct-current voltage input by the direct-current power supply; a transmitting chip connected to the primary coil of the RDL-based micro-transformer, and configured to receive the direct-current voltage, convert the direct-current voltage into an alternating current signal, and transmit the alternating current signal to a secondary coil of the RDL-based micro-transformer; and a receiving chip connected to the secondary coil of the RDL-based micro-transformer, and configured to convert the alternating current signal into a direct-current signal, generate a control signal for stabilizing the output voltage according to a change of a load, and encode the control signal for digital isolation. The present disclosure further provides a method of manufacturing an isolated power chip based on wafer level packaging.

This insulation module is provided with: a first conductor and a second conductor, which are buried in an insulating layer so as to face each other at a distance in the thickness direction of the insulating layer; a first electrode which is connected to the first conductor; a second electrode which is connected to the second conductor, while being arranged at a position that is away from the first electrode when viewed from the thickness direction of the insulating layer; a passivation layer which is formed on the surface of the insulating layer; a low dielectric constant layer which is formed on the surface of the passivation layer, and has a lower dielectric constant than the passivation layer; and a mold resin which covers the low dielectric constant layer.

A semiconductor module includes a wiring board having a semiconductor element mounted thereon, and a heat dissipation base bonded to the wiring board via a bonding material. In a cross section passing through corners both an insulating layer of the wiring board and a second conductor layer on the insulating layer in plan view, in a horizontal direction, a distance from the second conductor layer to a peripheral edge of the bonding material on the second conductor layer is equal to or less than a thickness of the bonding material between the second conductor layer and the heat dissipation base, and a distance from the second conductor layer to a non-bonded region provided on the heat dissipation base around the bonding material is equal to or less than a distance from the second conductor layer to a peripheral edge of the insulating layer on a second surface.

A semiconductor device includes first semiconductor chips that each include a first control electrode and a first output electrode, second semiconductor chips each include a second control electrode and a second output electrode, first and second input circuit patterns on which the first and second input electrodes are disposed, respectively, first and second control circuit patterns electrically connected to the first and second control electrodes, respectively, first and second resistive elements, and a first inter-board wiring member. The first control electrodes and first resistive element are electrically connected via the first control circuit pattern, the second control electrodes and second resistive element are electrically connected via the second control circuit pattern, and at least one of the first output electrodes and at least one of the second output electrodes are electrically connected to each other via the first inter-board wiring member.