A semiconductor device includes a low-density substrate, a high-density patch positioned inside a cavity in the low-density substrate, a first semiconductor die, and a second semiconductor die. The first semiconductor dies includes high-density bumps and low-density bumps. The second semiconductor die includes high-density bumps and low-density bumps. The high-density bumps of the first semiconductor die and the high-density bumps of the second semiconductor die are electrically connected to the high-density patch. The low-density bumps of the first semiconductor die and the low-density bumps of the second semiconductor die are electrically connected to the low-density substrate.

Methods of making a semiconductor device assembly are provided. The methods can comprise providing a first semiconductor device having a first dielectric material at a first surface, providing a carrier wafer having a second dielectric material at a second surface, and forming a dielectric-dielectric bond between the first dielectric material and the second dielectric material. At least one of the first surface and the second surface includes a cavity configured to entrap a gas during the formation of the bond. The method can further include stacking one or more second semiconductor devices over the first semiconductor device to form the semiconductor device assembly, and removing the semiconductor device assembly from the carrier wafer.

The invention relates to a method for the temporary bonding of a product substrate with a carrier substrate and for the debonding of a product substrate from a carrier substrate, corresponding devices and a substrate stack.

A chip based on a low-modulus supramolecular coating material includes a chip body and a low-modulus supramolecular coating provided on one side of the chip away from a growth substrate, wherein the chip body is of a cylindrical or columnar structure, the low-modulus supramolecular coating is completely or partially coated on a surface of the chip, and an area of the low-modulus supramolecular coating is less than or equal to an area of the chip body. The transfer substrate includes a substrate and a low-modulus supramolecular coating, wherein the low-modulus supramolecular coating is patterned and modified on a surface of the substrate to form a plurality of transfer sites, and a position and a size of each transfer site correspond to distribution and sizes of the transferred chips. The present application addresses problems such as complicated structures, relatively low transfer efficiency, poor precision and vulnerability of the transferred chips.

A micro-device substrate structure includes a support substrate having a support-substrate surface, spatially separated indentations extending into the support substrate, and a micro-device comprising a micro-device body and micro-device posts. The micro-device posts extend from the micro-device body into the support substrate and each of the posts is disposed at least partly in a different indentation. A release layer can be disposed between the micro-device posts and the support substrate. When the release layer is etched, the micro-device can be completely disconnected from the source substrate, removed from the indentations and source substrate, and micro-transfer printed to a target substrate.

A micro device mass transfer equipment including a base stage, a moving stage, a substrate stage, a laser device, a rolling and pressing mechanism, and a heating mechanism is provided. The moving stage is movably disposed on the base stage, and moves with a moving path. The substrate stage is movably disposed on the base stage, and is adapted to move between different positions overlapping the moving stage. The laser device is movably disposed on the base stage. The laser device is adapted to move relative to the substrate stage, and emits a laser beam toward the substrate stage. The rolling and pressing mechanism is disposed on the moving path of the moving stage, and forms a contact region with the moving stage. The heating mechanism is disposed corresponding to the contact region, and is adapted to heat the contact region between the moving stage and the rolling and pressing mechanism.

This disclosure is related to integrating pixelated microdevices into a system substrate to develop a functional system such as display, sensors, and other optoelectronic devices. The process may involve having a structure of release layers in the housing and then using different decoupling mechanisms for release. The release layers are not limited to but can be a combination of chemical or optical or mechanical release layers.

An electronic structure includes: a substrate having a first surface; a functional element unit including a functional element having an electronic function, and a protector covering the functional element, the functional element unit having a second surface facing the first surface; a support disposed between the first surface and the second surface, the support supporting the second surface; and a projection disposed on a first surface side of the substrate, the projection projecting toward the functional element unit. The support has a third surface in contact with the second surface of the functional element unit, the third surface having an area smaller than an area of the second surface. The projection has a fourth surface in contact with or close to the functional element unit, the fourth surface having an area smaller than the area of the second surface, the projection being formed by a different material from the support.

Various embodiments of the present technology provide for the ultra-high density heterogenous integration, enabled by nano-precise pick-and-place assembly. For example, some embodiments provide for the integration of modular assembly techniques with the use of prefabricated blocks (PFBs). These PFBs can be created on one or more sources wafers. Then using pick-and-place technologies, the PFBs can be selectively arranged on a destination wafer thereby allowing Nanoscale-aligned 3D Stacked Integrated Circuit (N3-SI) and the Microscale Modular Assembled ASIC (M2A2) to be efficiently created. Some embodiments include systems and techniques for the construction of construct semiconductor devices which are arbitrarily larger than the standard photolithography field size of 2633 mm, using pick-and-place assembly.

The present description concerns a process including the following steps: providing a plurality of assemblies, each including a donor substrate covered by a functional block successively including a first interconnection layer, a functional layer, and a second interconnection layer, the functional layer including one or more electronic components, the interconnection layers including a dielectric material in which are formed conductive elements, a first surface of the first interconnection layer in contact with the donor substrate and the free surface of the second interconnection layer being planarized so as to be compatible with a subsequent direct bonding, successively transferring, onto a receiver substrate the functional blocks, by direct bonding, to form a 3D assembly comprising a receiver substrate covered by a stack of two functional blocks.