H10P74/20

MICROFLUIDIC TRANSFER SUBSTRATE, MICROFLUIDIC TRANSFER DEVICE, AND MICROFLUIDIC TRANSFER APPARATUS
20260013286 · 2026-01-08 · ·

A microfluidic transfer substrate includes a plurality of pixel groups. Each pixel group includes at least three first pixel units, and the at least three first pixel units of each pixel group are arranged around a center point. One first pixel unit of each pixel group serves as a first microfluidic pixel and a surface of the first microfluidic pixel defines an assembly groove, and the other first pixel units of each pixel group serve as second microfluidic pixels and a surface of each second microfluidic pixel is free of the assembly groove. Each first pixel unit includes a thin film transistor, a microfluidic electrode layer, and a hydrophobic layer. A microfluidic transfer device and a microfluidic transfer apparatus are further provided.

System and method for monitoring chemical mechanical polishing

An apparatus for chemical mechanical polishing of a wafer includes a process chamber and a rotatable platen disposed inside the process chamber. A polishing pad is disposed on the platen and a wafer carrier is disposed on the platen. A slurry supply port is configured to supply slurry on the platen. A process controller is configured to control operation of the apparatus. A set of microphones is disposed inside the process chamber. The set of microphones is arranged to detect sound in the process chamber during operation of the apparatus and transmit an electrical signal corresponding to the detected sound. A signal processor is configured to receive the electrical signal from the set of microphones, process the electrical signal to enable detection of an event during operation of the apparatus, and in response to detecting the event, transmit a feedback signal to the process controller. The process controller is further configured to receive the feedback signal and initiate an action based on the received feedback signal.

Methods of determining a height, and a height profile, of a wire loop on a wire bonding machine

A method of determining a height value of a wire loop on a wire bonding machine is provided. The method includes the steps of: (a) imaging at least a portion of a wire loop using an imaging system on a wire bonding machine to detect a path of the portion of the wire loop; (b) moving a wire bonding tool towards a first contact portion of the wire loop in the path; (c) detecting when a portion of a conductive wire engaged with the wire bonding tool contacts the first contact portion of the wire loop; and (d) determining a height value of the wire loop at the first contact portion based on a position of the wire bonding tool when the portion of the conductive wire contacts the first contact portion of the wire loop.

Substrate inspection system and method of manufacturing semiconductor device using substrate inspection system

A substrate inspection apparatus includes a light source unit, a pulsed beam matching unit, a substrate support unit, an incidence angle adjusting unit, and a detecting unit. The light source unit emits first and second laser beams. The pulsed beam matching unit matches the first and second laser beams to superimpose a pulse of the first laser beam on a pulse of the second laser beam in time and space. The incidence angle adjusting unit adjusts angles of incidence of the matched first laser beam and second laser beams to irradiate the first laser beam and the second laser beam on the substrate, and mixes the first and second laser beams to generate an evanescent wave on the substrate. The evanescent wave generates scattered light due to a defect of the substrate. The detecting unit detects the scattered light generated due to the defect of the substrate.

Defect observation method, apparatus, and program

A defect observation method includes, as steps executed by a computer system, a first step of acquiring, as a bevel image, an image captured using defect candidate coordinates in a bevel portion as an imaging position by using a microscope or an imaging apparatus; and a second step of detecting a defect in the bevel image. The second step includes a step of determining whether there is at least one portion among a wafer edge, a wafer notch, and an orientation flat in the bevel image, a step of switching and selectively applying a defect detection scheme of detecting the defect from the bevel image from a plurality of schemes which are candidates based on a determination result, and a step of executing a process of detecting the defect from the bevel image in conformity with the switched scheme.

Wafer stacking method

A wafer stacking method includes the following steps. A first wafer is provided. A second wafer is bonded to the first wafer to form a first wafer stack structure. A first edge defect inspection is performed on the first wafer stack structure to find a first edge defect and measure a first distance in a radial direction between an edge of the first wafer stack structure and an end of the first edge defect away from the edge of the first wafer stack structure. A first trimming process with a range of a first width is performed from the edge of the first wafer stack structure to remove the first edge defect. Herein, the first width is greater than or equal to the first distance.

Method for aligning to a pattern on a wafer

A method for aligning to a pattern on a wafer is disclosed. The method includes the steps of obtaining a first inline image from a first sample wafer, obtaining a first contour pattern of an alignment mark pattern from the first inline image, using the first contour pattern to generate a first synthetic image in black and white pixels of only two grayscale levels, using the first synthetic image as a reference to recognize the alignment mark pattern on a tested wafer, and aligning to a tested pattern on the tested wafer according to a position of the alignment mark pattern on the tested wafer and a coordinate information.

Method and apparatus for substrate temperature control

Methods and apparatus for controlling substrate temperature includes: measuring a substrate that has undergone a deposition process; analyzing measurements of the substrate to detect a defect of the substrate; and sending a feedback signal to modify a temperature control parameter of a temperature controller used in controlling a temperature of the substrate in the deposition process based on the analyzing if a defect is detected, and not sending a feedback signal to modify the temperature control parameter if a defect is not detected.

Integrated inspection for enhanced hybrid bonding yield in advanced semiconductor packaging manufacturing

Methods and apparatus of hybrid bonding with inspection are provided herein. In some embodiments, a method of hybrid bonding with inspection includes: cleaning a substrate via a first cleaning chamber and a tape frame having a plurality of chiplets via a second cleaning chamber; inspecting, via a first metrology system, the substrate for pre-bond defects in a first metrology chamber and the tape frame for pre-bond defects in a second metrology chamber; bonding one or more of the plurality of chiplets to the substrate via a hybrid bonding process in a bonder chamber to form a bonded substrate; and performing, via a second metrology system different than the first metrology system, a post-bond inspection of the bonded substrate via a third metrology chamber for post-bond defects.

Method for testing the stress robustness of a semiconductor substrate

A method tests the stress robustness of a semiconductor substrate. The method includes: forming a nitride layer on a surface of the semiconductor substrate, the nitride layer being directly deposited on the surface of the semiconductor substrate or on a native oxide layer that is interposed on the surface; cooling the semiconductor substrate and the nitride layer; patterning the nitride layer into a patterned nitride by photolithography including a step of reactive ion etching with ions produced from a gas, which includes hydrogen or a hydrogen compound or both; processing the patterned nitride and the semiconductor substrate at a temperature of not less than 800 C. and not more than 1300 C. in a nitrogen atmosphere to induce the formation of dislocations at an interface between the patterned nitride and the semiconductor substrate; and evaluating at least one property that is related to the formed dislocations.