A standby current detection circuit includes multiple first transistors. The first transistors are coupled in series to form a first detection circuit string, where N is a positive integer. The first detection circuit string is disposed on a scribe lane of a wafer, and the first detection circuit string is operated in a standby state and serves as a test medium for a standby current.

Embodiments herein are directed to localized wafer thickness correction. In some embodiments, a method may include providing a substrate including an upper surface having a raised portion extending above a plane defined by the upper surface, and a non-raised portion adjacent the raised portion. The method may further include performing a metrology scan of the upper surface to determine a first dimension of the raised portion and a second dimension of the non-raised portion, and depositing a hardmask over the upper surface, including over the raised portion and the non-raised portion. The method may further include directing ions to the hardmask, wherein a first dose of the ions over the raised portion is greater than a second dose of the ions over the non-raised portion, and performing a first etch to the hardmask to remove the hardmask over the raised portion, wherein the hardmask remains over the non-raised portion.

A pickup control method and a transfer device of a light-emitting element chip are discussed. The pickup control method can include a first operation of loading stamps on a transfer head, transporting the transfer head to a first substrate, and picking up light-emitting element chips with the stamps, a second operation of transporting the transfer head along with the stamps that pick up the light-emitting element chips to a second substrate and checking pickup states of the light-emitting element chips transported to the second substrate using an image detector located below the transfer head, and a third operation of transporting the transfer head along with the stamps that pick up the light-emitting element chips toward a chip removal system when a pickup failure is detected from the light-emitting element chips as a result of analyzing an image captured by the image detector.

Methods and systems for measurements of semiconductor structures based on a trained parameter conditioned measurement model are described herein. The shape of a measured structure is characterized by a geometric model parameterized by one or more conditioning parameters and one or more non-conditioning parameters. A trained parameter conditioned measurement model predicts a set of values of each non-conditioning parameter based on measurement data and a corresponding set of predetermined values for each conditioning parameter. In this manner, the trained parameter conditioned measurement model predicts the shape of a measured structure. Although a parameter conditioned measurement model is trained at discrete geometric points of a structure, the trained model predicts values of non-conditioning parameters for any corresponding conditioning parameter value. In some examples, training data is augmented by interpolation of conditioning parameters and corresponding non-conditioning parameters that lie between discrete DOE points. This improves prediction accuracy of the trained model.

An object of the present invention is to provide a novel evaluation method suitable for evaluating a SiC substrate having a large diameter. The present invention is a method for evaluating a silicon carbide substrate, the method comprising an image acquisition step of acquiring an image by making an electron beam incident at an incident angle inclined with respect to a normal line of a {0001} plane of a silicon carbide substrate, wherein the incident angle is 10 or less.

A fabricating method for a test element group is provided. The fabricating method for a test element group includes fabricating test areas generated in a scribe lane area, wherein fabricating of the test areas includes forming a plurality of fins protruding in a first direction on a substrate, covering at least some of the plurality of fins with a masking material, and performing selective epitaxial growth by injecting a gas onto the plurality of fins. The gas is not injected onto the at least some of the plurality of fins that are covered with the masking material, such that the epitaxial growth does not occur on the fins covered with the masking material.

A sample that includes a target structure with a structure-of-interest (SOI) having a set of known parameters optically coupled to an unknown structure, e.g., having unknown parameters, is optically measured using light that is incident on the target structure. Light detected from the target structure in response to the incident illumination light incident is used to obtain metrology data, which is a combination of a from the SOI and a contribution from the unknown structure. A set of parameter values characterizing the SOI and a set of parameter values characterizing the unknown structure are determined from a trained neural network based on the metrology data.

Methods and pad structures to test via accuracy are provided. A method according to the present disclosure includes forming a first pad and a second pad on a device component, wherein the second pad includes a via landing area and a clearance opening, providing a core substrate that includes a cavity, placing the device component in the cavity, forming a build-up film over the device component and the core substrate, forming a first contact via extending through the build-up film to contact the landing area and a second contact via extending through build-up film and the clearance opening, and performing a continuity test to determine whether the second contact via is in contact with the second pad.

A trench gate type IGBT includes a plurality of trenches, including a plurality of gate trenches having a gate region inside, and a plurality of emitter trenches having an emitter region connected to an emitter electrode. A mesa section adjacent to the trench has a second mesa region, which does not function as a channel; and a contact, which connects the emitter electrode; the second mesa region being sandwiched between the gate trench and the emitter trench.

An arrangement device includes: a detector obtaining an image in a field of view (FOV) of a wafer, and a processor digitalizing the obtained image into black and white to model an edge line, and identifying a central position of the wafer by using the modeled edge line. The processor stores three reference points placed at half of a width and half of a height of the FOV, and obtains the image at each of the three reference points.