A device includes a semiconductor substrate, and a plurality of semiconductor fins parallel to each other, wherein the plurality of semiconductor fins is a portion of the semiconductor substrate. A Shallow Trench Isolation (STI) region is on a side of the plurality of semiconductor fins. The STI region has a top surface and a non-flat bottom surface, wherein the plurality of semiconductor fins is over the top surface of the STI region.

The present disclosure relates to semiconductor structures and, more particularly, to single diffusion cut for gate structures and methods of manufacture. The structure includes a single diffusion break extending into a substrate between diffusion regions of adjacent gate structures, the single diffusion break filled with an insulator material and further comprising an undercut region lined with a liner material which is between the insulator material and the diffusion regions.

Devices and methods of manufacture for a deep trench layout area-saving semiconductor structure for use with bipolar-CMOS-DMOS (BCD) devices. A semiconductor device may comprise a first BCD device formed within a first perimeter of a first BCD layout area, and a deep trench isolation structure defining the first perimeter of the first BCD layout area, in which the deep trench isolation structure may comprise a first rounded corner that may define a first corner of the first BCD layout area. A semiconductor device may comprise, a substrate, BCD device formed on the substrate, and a deep trench isolation structure laterally surrounding the BCD device. The deep trench isolation structure, with respect to a top-down view, may comprise vertical portions, horizontal portions, a T-shaped intersection connecting at least one vertical portion and at least one horizontal portion, and a cross-shaped intersection connecting two vertical portions and two horizontal portions.

A method for forming a charge balance region in a semiconductor device includes: providing an epitaxial layer on a substrate, whereby a diffusion layer is formed between the substrate and the epitaxial layer; forming a plurality of recessed features extending in a vertical direction in the epitaxial layer and laterally spaced apart from one another; forming an insulating layer on at least sidewalls of each of the recessed features; and forming a resistive film on the insulating layer and a bottom of each of the recessed features using atomic layer deposition. The resistive film is configured to provide a conductive path between an upper surface of the epitaxial layer and one of the diffusion layer, a lower portion of the epitaxial layer, or the substrate, whereby a current flowing through the resistive film fully depletes at least a portion of the epitaxial layer between adjacent recessed features.

A middle voltage transistor with a fin structure includes a substrate. A fin structure protrudes from a surface of the substrate. A gate structure crosses the fin structure. A source is disposed at one side of the gate structure and embedded in the fin structure, and a drain is disposed at the other side of the gate structure and embedded in the fin structure. A second deep trench isolation is embedded in the substrate and adjacent to the source and drain. An isolation structure is embedded in the fin structure below the gate structure. The isolation structure includes a first deep trench isolation and a first shallow trench isolation extending from a sidewall of the first deep trench isolation toward the source.

An integrated circuit includes a first nanostructure transistor and a second nanostructure transistor. The first and second nanostructure each include gate electrodes. A backside trench separates the first gate electrode from the second gate electrode. A bulk dielectric material fills the backside trench. A gate cap metal electrically connects the first gate electrode to the second gate electrode.

Methods, systems, and devices for selective cavity merging for isolation regions in a memory die are described. For example, formation of material structures of a memory die may include depositing a stack of alternating layers of a first material and a second material over a substrate of the memory die, forming a pattern of cavities through the stack of alternating material layers, and forming voids between layers of the first material based on removing portions of the second material. An electrical isolation region may be formed between portions of the memory die based on depositing a dielectric material in at least some of the cavities and in at least a portion of the voids between the layers of the first material.

A high-voltage transistor may include a composite gate dielectric layer having multiple regions with different dielectric constant values and/or a composite gate structure having multiple regions of different work function values. The composite dielectric layer having multiple regions with different dielectric constant values and/or the composite gate structure having multiple regions with different work functions increases the threshold voltage uniformity across a channel region of the high-voltage transistor. The increased threshold voltage uniformity may enable a low subthreshold swing and a low subthreshold off-stage current leakage to be achieved for the high-voltage transistor, which increases the operating efficiency of the high-voltage transistor and enables the size of the high-voltage transistor to be reduced without increasing (or with minimal increase to) the subthreshold swing and and/or the subthreshold off-stage current leakage of the high-voltage transistor.

For manufacturing a memory device, a system may form a trench between a first portion and a second portion of a stack. A bottom wall of the trench may include a spacer material. The system may remove a first and a second oxide material to reform the trench, and remove a polysilicon material in a lateral direction to expose a third oxide material and a channel structure. The third oxide material may form the bottom wall of the trench. The system may remove, in a lateral direction, the first oxide material, a portion of the second oxide material, the third oxide material, and a fourth oxide material of the channel structure. The system may deposit a metal material, in the trench, in contact with a doped polysilicon material of the channel structure.

The present disclosure relates to methods, devices, and systems for managing isolating structures in semiconductor devices. An example semiconductor device includes a first stack of conductive layers and isolating layers extending along a first direction and alternating with each other along a second direction perpendicular to the first direction. The semiconductor device further includes a gate line slit structure extending through the first stack along the second direction, and a first isolating structure extending along the first direction. The first isolating structure includes a first portion in the first stack and a second portion in the gate line slit structure. A size of the first portion is greater than a size of the second portion along the second direction.