A package structure includes a leadframe, at least two dies, at least one spacer and a plastic package material. The leadframe includes a die pad. The dies are disposed on the die pad of the leadframe. The spacer is disposed between at least one of the dies and the die pad. The plastic package material is disposed on the leadframe, and covers the dies. A first minimum spacing distance is between one of a plurality of edges of the spacer and one of a plurality of edges of the die pad, a second minimum spacing distance is between one of a plurality of edges of the dies and one of the edges of the die pad, and the first minimum spacing distance is larger than the second minimum spacing distance.

An electronic package is provided, in which an electronic element is arranged on a carrier structure having a plurality of wire-bonding pads arranged on a surface of the carrier structure, and a plurality of bonding wires are connected to a plurality of electrode pads of the electronic element and the plurality of wire-bonding pads. Further, among any three adjacent ones of the plurality of wire-bonding pads, a long-distanced first wire-bonding pad, a middle-distanced second wire-bonding pad and a short-distanced third wire-bonding pad are defined according to their distances from the electronic element. Therefore, even if the bonding wires on the first to third wire-bonding pads are impacted by an adhesive where a wire sweep phenomenon occurred when the flowing adhesive of a packaging layer covers the electronic element and the bonding wires, the bonding wires still would not contact each other, thereby avoiding short circuit problems.

Provided is a semiconductor package including a package substrate having a first upper connection pad and a second upper connection pad provided on a top surface of the package substrate, a semiconductor chip disposed on the package substrate, a second semiconductor chip provided on the first semiconductor chip, a plurality of first chip pads and a plurality of second chip pads provided on top surfaces of the first semiconductor chip and the second semiconductor chip, respectively, a plurality of first conductive patterns, a plurality of second conductive patterns, and a cross conductive pattern of which both ends are connected to the first conductive pattern, wherein the cross conductive pattern is provided on a top surface of the first semiconductor chip and the second conductive pattern, and the cross conductive pattern crosses the second cross conductive pattern.

A semiconductor package includes a package substrate having substrate pads disposed in a first direction on one surface, a semiconductor chip having chip pads disposed in the first direction, and bonding wires connecting the chip pads and the substrate pads. The bonding wires include first and second bonding wires alternately connected to the substrate pads respectively, in the first direction, the first bonding wires are connected to the substrate pads at a first angle less than a right angle with respect to a direction of the semiconductor chip, the second bonding wires are connected to the substrate pads at a second angle less than the first angle with respect to the direction of the semiconductor chip and a position at which the first bonding wires contact the substrate pads is closer to the semiconductor chip than a position at which the second bonding wires contact the substrate pads is to the semiconductor chip.

A semiconductor package includes a package substrate including first and second power P-pads and first and second signal P-pads, a lower layer chip including first and second power L-pads and first and second signal L-pads, an upper layer chip offset from the lower layer chip and including first and second power U-pads and first and second signal U-pads. The first power and signal P-pads are alternatingly stacked, the first power and signal L-pads are alternatingly stacked, and the first power and signal U-pads are alternatingly stacked. The second power and signal P-pads are alternatingly stacked, the second power and signal L-pads are alternatingly stacked, and the second power and signal U-pads are alternatingly stacked. Bonding wires connect the first and second power U-pads, the first and second power L-pads, the second power U-pads and P-pads, and the second signal U-pads and P-pads.

A sensor package structure includes a substrate, a sensor chip disposed on the substrate, a plurality of first metal wires, a plurality of second metal wires, a ring-shaped supporting layer formed on the sensor chip, and a light-permeable sheet. The first metal wires and the second metal wires are connected to the substrate and the sensor chip. Each edge of a top surface of the sensor chip is provided with at least one of the second metal wires adjacent thereto. Each of the second metal wires has a highest endpoint that is higher than a highest endpoint of any one of the first metal wires with respect to the substrate, and the light-permeable sheet is disposed on the ring-shaped supporting layer and abuts against the highest endpoints of the second metal wires, such that the first metal wires are not in contact with the light-permeable sheet.

A method for manufacturing a light emitting device includes: preparing a first substrate having an upper surface comprising an element placement region; placing a light emitting element in the element placement region; disposing an uncured, sheet-like light-transmissive member on the light emitting element and bringing an outer edge of a lower surface of the light-transmissive member into contact with an outer upper surface of the element placement region of the first substrate by pressing the light-transmissive member; and disposing a first protrusion portion along an outer edge of an upper surface of the light-transmissive member so that the first protrusion portion extends over the upper surface of the first substrate and the upper surface of the light-transmissive member.

A semiconductor package includes a leadframe having a die pad and a plurality of pins disposed around the die pad, a metal interposer attached to a top surface of the die pad, and a semiconductor die attached to a top surface of the metal interposer. A plurality of bond wires with same function is bonded to the metal interposer. The die pad, the metal interposer and the semiconductor die are stacked in layers so as to form a pyramidal stack structure.

An IC package includes an interconnect having a first platform and a second platform that are spaced apart. The IC package includes a die superposing a portion of the first platform of the interconnect. The die has a field effect transistor (FET), and a matrix of pads for the FET situated on a surface of the die. The matrix of pads having a row of source pads and a row of drain pads. A drain wire bond extends from a first drain pad to a second drain pad of the row of drain pads and to the first platform of the interconnect. A source wire bond extends from a first source pad to a second source pad of the row of source pads, back over the first source pad and is coupled to a connection region of the first platform.

The disclosure describes a semiconductor device and a method for fabricating a semiconductor device. The semiconductor device includes: a first module and a second module stacked vertically on the first module, each module includes multiple dies stacked vertically within an insulation layer, wherein each die higher than a lower die is laterally offset from the lower die forming a terraced structure, wherein the second module comprises vertical wires connecting the overhang portions of the terraced structure of the second module to a top dielectric layer of the first module underneath the second module, and the insulation layer of the first module further includes through-insulation vias (TIVs) connecting the top dielectric layer to a bottom dielectric layer through the insulation layer, such that the dies of the second module are coupled to the bottom dielectric layer of the first module through the top dielectric layer and TIVs.