The present disclosure describes a method to form silicon germanium (SiGe) source/drain epitaxial stacks with a boron doping profile and a germanium concentration that can induce external stress to a fully strained SiGe channel. The method includes forming one or more gate structures over a fin, where the fin includes a fin height, a first sidewall, and a second sidewall opposite to the first sidewall. The method also includes forming a first spacer on the first sidewall of the fin and a second spacer on the second sidewall of the fin; etching the fin to reduce the fin height between the one or more gate structures; and etching the first spacer and the second spacer between the one or more gate structures so that the etched first spacer is shorter than the etched second spacer and the first and second etched spacers are shorter than the etched fin. The method further includes forming an epitaxial stack on the etched fin between the one or more gate structures.

A semiconductor device structure and a formation method are provided. The method includes forming multiple sacrificial layers and multiple semiconductor layers laid out in an alternating manner on a substrate. The method also includes partially removing the sacrificial layers and the semiconductor layers to form a recess exposing side edges of the sacrificial layers and the semiconductor layers. The method further includes forming p-type doped epitaxial structures on the side edges of the semiconductor layers and forming a germanium-containing epitaxial structure wrapped around the p-type doped epitaxial structures. The germanium-containing epitaxial structure has a higher atomic concentration of germanium than that of the p-type doped epitaxial structures. In addition, the method includes removing the sacrificial layers to release multiple semiconductor nanostructures constructed by remaining portions of the semiconductor layers and forming a metal gate stack wrapped around each of the semiconductor nanostructures.

A workpiece includes a doped p-type substrate, a co-doped P+ epitaxial silicon layer disposed on the doped p-type substrate, and a boron-doped P epitaxial layer disposed on the co-doped P+ epitaxial silicon layer. The co-doped P+ epitaxial silicon layer is co-doped with germanium and boron. A ratio of the germanium to the boron in the co-doped P+ epitaxial silicon layer may be from 10 to 16.

The present invention relates to a layer formation method and, more specifically, to a semiconductor device manufacturing method for forming a semiconductor device through a low-temperature process. The layer formation method according to an embodiment of the present invention is a method for manufacturing a semiconductor device which comprises a silicon substrate containing germanium (Ge) or a substrate on which a silicon layer containing germanium (Ge) is formed, and which comprises an undoped gallium nitride (GaN) layer, an N-type gallium nitride (GaN) layer, an active layer and a P-type gallium nitride (GaN) layer, wherein a step of forming at least one gallium nitride layer from among the undoped gallium nitride (GaN) layer, the N-type gallium nitride (GaN) layer, the active layer and the P-type gallium nitride (GaN) layer comprises the steps of: a) sequentially supplying a gallium (Ga) precursor and a nitrogen (N2) precursor at 500 C. or lower, thereby forming a gallium nitride (GaN) layer on the substrate; and b) exposing the gallium nitride (GaN) layer to a hydrogen-containing plasma, and steps a) and b) are repeated multiple times.

A method includes providing a substrate, a semiconductor fin extending from the substrate, and a gate structure over the substrate and engaging the semiconductor fin; etching the semiconductor fin to form a trench; and epitaxially growing a semiconductor structure in the trench, which includes epitaxially growing a first semiconductor layer having silicon germanium (SiGe); epitaxially growing a second semiconductor layer having SiGe above the first semiconductor layer; epitaxially growing a third semiconductor layer having SiGe over the second semiconductor layer; and epitaxially growing a fourth semiconductor layer having SiGe and disposed at a corner portion of the semiconductor structure. Each of the first, second, third, and fourth semiconductor layers includes a p-type dopant, and the fourth semiconductor layer has a higher dopant concentration of the p-type dopant than each of the first, second, and third semiconductor layers.

A fin structure on a substrate is disclosed. The fin structure can comprises a first epitaxial region and a second epitaxial region separated by a dielectric region, a merged epitaxial region on the first epitaxial region and the second epitaxial region, an epitaxial buffer region on a top surface of the merged epitaxial region, and an epitaxial capping region on the buffer epitaxial region and side surfaces of the merged epitaxial region.

A semiconductor device includes a first III-V nitride-based layer, a second III-V nitride-based layer, a nitride-based transition layer, and a nitride-based transistor. The first III-V nitride-based layer is disposed over a substrate by applying a first V/III ratio in a first range. The second III-V nitride-based layer is disposed over the first III-V nitride-based layer by applying a second V/III ratio in a second range, in which the first range and the second range are mutually exclusive. The nitride-based transition layer is disposed between the first III-V nitride-based layer and the second III-V nitride-based layer to connect the first III-V nitride-based layer with the second III-V nitride-based layer, in which the nitride-based transition layer is formed by applying a third V/III ratio in a third range between the first range and second range. The nitride-based transistor is disposed over the second III-V nitride-based layer.

Utility of an ECR plasma technique is enhanced. A film forming apparatus 1 deposits, on a surface of a substrate SUB, first target particles emitted by bombardment of ions (ions making ECR plasma) with a cylindrical target TA mounted on a cylindrical-target mounting section 27 and second target particles emitted by bombardment of ions (ions making plasma which is different in density from the ECR plasma) with a disk target TA2 mounted on a disk-target mounting section 31.

Deep trench isolation structures for high voltage semiconductor-on-insulator devices are disclosed herein. An exemplary deep trench isolation structure surrounds an active region of a semiconductor-on-insulator substrate. The deep trench isolation structure includes a first insulator sidewall spacer, a second insulator sidewall spacer, and a multilayer silicon-comprising isolation structure disposed between the first insulator sidewall spacer and the second insulator sidewall spacer. The multilayer silicon-comprising isolation structure includes a top polysilicon portion disposed over a bottom silicon portion. The bottom polysilicon portion is formed by a selective deposition process, while the top polysilicon portion is formed by a non-selective deposition process. In some embodiments, the bottom silicon portion is doped with boron.

A method for growing a III-V material may include forming at least one layer on a stack including a crystalline layer made of III-V material, a first masking layer surmounting the germination layer, the first masking layer having at least one first opening; depositing a second masking layer covering an upper face of the sacrificial layer; forming at least one second opening in the second masking layer; removing the sacrificial layer selectively at the first masking layer and at the second masking layer; epitaxially growing a material made of the III-V material from the germination layer; forming al least one third opening in the second masking layer; and epitaxially growing at least one material made of the III-V material from the first epitaxial layer.