An output matching circuit includes a transformer having one end electrically connected to an output terminal of a power amplifier element that amplifies an input signal and another end electrically connected to a terminal connected to a load, and converting an impedance of the terminal connected to the load to an impedance higher than an impedance of the output terminal, a first filter circuit that attenuates a signal within a first frequency band higher than a transmission frequency band of the input signal, and a second filter circuit that attenuates a signal within a second frequency band higher than the first frequency band.

A packaging device is provided. The packaging device includes a die disposed over a laminate, the die comprising a first via structure, and an interposer disposed between the die and the laminate. The interposer includes a second via structure. The packaging device also includes a lid disposed over the interposer and covering the die, a first patterned conductive layer disposed between the die and the interposer, and between the lid and the interposer; and a second patterned conductive layer disposed between the laminate and the interposer. The first patterned conductive layer includes a bonding structure electrically and thermally connected to the first via structure and the second via structure.

Design and construction of high interconnection density, minimal loss I/O channels comprising embedded passive networks that preserve signal integrity at signaling frequencies above 1 GHz, preferably above 10 GHz, to improve memory-processor bandwidths.

A three-dimensional (3D) metal-insulator-metal capacitor (MIMCAP) includes a plurality of center studs disposed within cavity walls of a plurality of cavities in a top plate. The center studs and the cavity walls are oriented orthogonal to a first metal layer and extend through a first via layer and a second metal layer. Each center stud includes a metal layer stud in the second metal layer stacked on a via layer stud in the first via layer. A dielectric layer is disposed between the center studs and the cavity walls of the plurality of cavities in the top plate. The center studs are coupled to a first electrode, and the top plate is coupled to a second electrode in the interconnect layers. In some examples, the center studs can form vertically oriented cylindrical capacitive elements positioned for high capacitance density.

A packaged module can include a packaging substrate with first and sides, first and second components mounted on the first and second sides, respectively, and first and second overmolds implemented on the first and second sides, respectively, with the second overmold defining a mounting surface. The packaged module can further include a plurality of conductive features implemented on the second side of the packaging substrate to provide electrical connections for the packaged module, with the conductive features being formed from conductive material having a sufficiently high melting temperature so that the conductive features do not melt during a mounting operation. Each conductive feature can have a surface that is substantially coplanar with or recessed with respect to the mounting surface, and a solderable material layer can be dimensioned to cover the surface of each conductive feature.

A method of fabricating an electronic device includes forming a multilevel package substrate, a semiconductor die, and a package structure, the multilevel package substrate having a first level, a second level, and a filter circuit in the first and second levels. The filter circuit includes a filter input terminal, a first capacitor, a first inductor, a second capacitor, a second inductor, a filter output terminal, and a reference terminal. The semiconductor die is attached to the multilevel package substrate and has a conductive structure coupled to one of the terminals of the filter circuit, and the package structure encloses the semiconductor die and a portion of the multilevel package substrate.

Embodiments disclosed herein include electronic packages In an embodiment, the electronic package comprises first substrate layers, and a core under the first substrate layers. In an embodiment, second substrate layers are under the core, and an interconnect is through the first substrate layers, the core, and the second substrate layers. In an embodiment, a portion of the interconnect through the second substrate layers comprises a pad, and a plurality of vias extending away from the pad.

In accordance with disclosed embodiments, there is an antenna package using a ball attach array to connect an antenna and base substrates of the package. One example is an RF module package including an RF antenna package having a stack material in between a top and a bottom antenna layer to form multiple antenna plane surfaces, a base package having alternating patterned conductive and dielectric layers to form routing through the base package, and a bond between a bottom surface of the antenna package and to a top surface of the base package.

An antenna device includes substrate layers, metallic layers, a non-shielding channel, an electronic component, a shielding layer and an antenna unit. The substrate layers include an upper substrate layer and a lower substrate layer located on two sides respectively. The metallic layers are disposed on the substrate layers. The non-shielding channel is at least defined at the upper substrate layer and communicates with the inner and outer surfaces of the upper substrate layer without being interfered by the first metallic layer. The electronic component is disposed on the outer surface of the upper substrate layer and corresponds to and at least partially covers the non-shielding channel. The shielding layer electrically shields the electronic component and is electrically connected to the first metallic layer. The antenna unit is disposed on an outer surface of the lower substrate layer and electrically coupled to the electronic component.

An electronic package and a manufacturing method thereof are provided, in which an electronic element is disposed on a carrier structure with a circuit layer, a first encapsulating layer and a second encapsulating layer are formed on the carrier structure to cover the electronic element, a first antenna layer is formed on the first encapsulating layer, and a second antenna layer communicatively connected to the first antenna layer is formed on the second encapsulating layer. Therefore, the thickness of the first encapsulating layer is used to control the resonance distance of the antenna frequency so as to generate better resonance effect, and the distance between the first antenna layer and the second antenna layer is controlled by the thickness of the second encapsulating layer to increase the bandwidth of the antenna.