A method for etching a dielectric layer covering a top and a flank of a three-dimensional structure, this method including a first etching of the dielectric layer, including a first fluorine based compound, a second compound taken from SiwCl(2w+2) and SiwF(2w+2), oxygen, this first etching being carried out to form a first protective layer on the top and form a second protective layer on the dielectric layer, a second etching configured to remove the second protective layer while retaining a portion of the first protective layer, the first and second etchings being repeated until removing the dielectric layer located on the flank of the structure. The second etching can be carried out by hydrogen-based plasma.

A substrate processing method processes a substrate. The substrate has a major surface including a concave-portion forming surface that forms a concave portion. A to-be-removed layer is formed in the concave portion. The substrate processing method includes an etching step of supplying an etching liquid that contains etching ions to the major surface of the substrate to etch the to-be-removed layer, a concentrating step of concentrating the etching liquid on the major surface of the substrate, a hydrophilizing step of hydrophilizing the concave-portion forming surface exposed by concentrating the etching liquid, an ion diffusing step of diffusing the etching ions into a rinsing liquid by supplying the rinsing liquid to the major surface of the substrate after the hydrophilizing step, and a rinsing liquid removing step of removing the rinsing liquid from the major surface of the substrate.

A substrate processing method according to the present invention incudes: a preparation step of preparing a substrate in which at least a first surface containing silicon oxide and a second surface containing silicon or a silicon compound other than silicon oxide are exposed; a surface modification step of forming an etching selectivity imparting film on at least a part of the first surface and at least a part of the second surface by a silylation treatment of bringing a silylating agent into contact with the first surface and the second surface; and an etching step of selectively carrying out an etching treatment on the second surface with respect to the first surface using an etching agent after the surface modification step.

Methods of forming contacts for source/drain regions and a contact plug for a gate stack of a finFET device are disclosed herein. Methods include etching a contact opening through a dielectric layer to expose surfaces of a first source/drain contact and repairing silicon oxide structures along sidewall surfaces of the contact opening and along planar surfaces of the dielectric layer to prevent selective loss defects from occurring during a subsequent selective deposition of conductive fill materials and during subsequent etching of other contact openings. The methods further include performing a selective bottom-up deposition of conductive fill material to form a second source/drain contact. According to some of the methods, once the second source/drain contact has been formed, the contact plug may be formed over the gate stack.

A method for manufacturing a semiconductor structure and a semiconductor structure are disclosed. The method includes the steps as follows. A substrate is provided, where the substrate includes a first region and a second region. A stacked structure with multiple first material layers and multiple second material layers alternately stacked is formed on the first region. First etching is performed to form a groove at one end of the stacked structure, the second region being exposed at the bottom of the groove. Second etching is performed, to remove a part of the multiple second material layers through the groove, and retain the multiple first material layers arranged at intervals. Before the second etching is performed, the method further includes the step as follows. A protective layer is formed on a surface of the second region, where the protective layer further extends toward at least a surface of the first region.

A method for manufacturing a silicon substrate for a quantum computer, the method includes the steps of forming a Si epitaxial layer by epitaxial growth using a Si source gas as a silicon-based raw material gas, in which a total content of 28Si and 30Si in a whole silicon contained in the silicon-based raw material gas is 99.9% or more, on a silicon substrate, forming an oxygen (O) -doped layer by oxidizing a surface of the Si epitaxial layer, and forming a Si epitaxial layer by epitaxial growth using a Si source gas, in which a total content of 28Si and 30Si in a whole silicon contained in the silicon-based raw material gas is 99.9% or more, on the -doped layer.

A method for manufacturing a support substrate comprising a charge-trapping layer for a semiconductor-on-insulator or piezoelectric-on-insulator structure for a radio-frequency application, includes: placing a base substrate comprising a layer of native silicon oxide in a deposition chamber; raising the temperature of the deposition chamber to a deposition temperature of the charge-trapping layer; introducing an oxidizing gas into the deposition chamber in order to preserve the layer of native silicon oxide during the temperature rise; venting the oxygen from the deposition chamber at the formation temperature of the charge-trapping layer; and-depositing, in the deposition chamber, the charge-trapping layer of polycrystalline silicon on the layer of native silicon oxide.

The present application provides a method for improving continuity of a work function thin film, forming a tunneling oxide layer on a substrate; forming an isolation layer on the tunneling oxide layer; forming a work function thin film on the isolation layer, the work function thin film serves as a floating gate in a semi-floating gate device to store charges and conduction electrons, performing a heat treatment on the tunneling oxide layer, the isolation layer and the work function layer, the isolation layer reacts with a surface of the tunneling oxide layer to form a dense barrier layer, the isolation layer reacts with O in the tunneling oxide layer to form a new tunneling oxide layer, the heat treatment lasts until the isolation layer is fully consumed, and the work function thin film remaining after the reaction uniformly covers an upper surface of the dense barrier layer.

A method for fabricating semiconductor device includes the steps of: forming fin-shaped structures on a substrate; using isopropyl alcohol (IPA) to perform a rinse process; performing a baking process; and forming a gate oxide layer on the fin-shaped structures. Preferably, a duration of the rinse process is between 15 seconds to 60 seconds, a temperature of the baking process is between 50 C. to 100 C., and a duration of the baking process is between 5 seconds to 120 seconds.

A layered structure can include a porous layer over a substrate and a thermal layer coupled to pore walls of the porous layer. The porous layer can have a higher resistivity than the substrate. A stress of the porous layer can be proportional to a variance of infrared (IR) transmission data of the porous layer. The variance of IR transmission data can be no greater than 2,500. Advantageously the thermal layer can decrease stress in the porous layer, increase thermal stability of the porous layer, decrease cracking and flaking during high temperature processing, maintain high resistivity of the porous layer, and increase the quality of the epitaxial layer and/or semiconductor devices formed using the porous layer.