A nitride semiconductor device includes an amorphous glass substrate having a first surface and a second surface opposite the first surface, a buffer layer provided on the first surface of the amorphous glass substrate, and a nitride semiconductor laminate including at least one gallium nitride layer disposed on the buffer layer. The first surface of the amorphous glass substrate has an uneven structure comprising a convex surface having a flat top portion and a concave surface having a flat bottom portion. The buffer layer and the nitride semiconductor laminate are disposed on the uneven structure.

A semiconductor structure and a method of forming the same are provided. In an embodiment, an exemplary method includes forming a source/drain opening extending through of a fin-shaped active region that comprises a plurality of channel layers interleaved by a plurality of sacrificial layers, replacing the plurality of sacrificial layers with a plurality of dielectric layers, recessing the plurality of dielectric layers to form inner spacer recesses, forming inner spacer features in the inner spacer recesses, where a bottommost inner spacer feature of the inner spacer features is thicker than one inner spacer feature of the inner spacer features disposed over the bottommost inner spacer feature, forming an isolation layer in the source/drain opening, and forming a source/drain feature in the source/drain opening and over the isolation layer, wherein the source/drain feature is spaced apart from the isolation layer by an air gap.

The present disclosure has an object of providing a method of manufacturing a semiconductor device whose manufacturing processes can be simplified. The method of manufacturing the semiconductor device according to the present disclosure includes: a preparation process of preparing two crystalline substrates made of silicon carbide and having respective constant thicknesses; a laminating process of laminating the two crystalline substrates to form a laminated crystalline substrate; an epitaxial growth process of forming an epitaxial layer on a first main surface of the laminated crystalline substrate; an element forming process of forming an element on the epitaxial layer; and a grinding process of grinding, after the element forming process, the laminated crystalline substrate from a second main surface of the laminated crystalline substrate to grind an interface between the laminated two crystalline substrates, the second main surface facing the first main surface.

A support substrate for a radiofrequency application comprises: a base substrate made of monocrystalline silicon comprising P-type dopants and having a resistivity that is greater than or equal to 250 ohm.Math.cm and strictly less than 500 ohm.Math.cm, and a content of interstitial oxygen between 13 ppma and 19 ppma, an epitaxial layer made of monocrystalline silicon comprising P-type dopants, disposed on the base substrate and having a thickness between 2 microns and 30 microns, an upper portion at least of the epitaxial layer having a resistivity greater than 3000 ohm.Math.cm, a charge-trapping layer made of polycrystalline silicon having a resistivity greater than or equal to 1000 ohm.Math.cm and a thickness between 1 micron and 10 microns. A method is used for manufacturing such a support substrate.

According to one embodiment, a semiconductor device includes a first electrode, a second electrode, a third electrode, a first nitride region, a second nitride region, and a third nitride region. The first nitride region includes Al.sub.x1Ga.sub.1-x1N (0x1<1). The first nitride region includes a first partial region, a second partial region, a third partial region, a fourth partial region, and a fifth partial region. The second nitride region includes Al.sub.x2Ga.sub.1-x2N (x1<x21) or In.sub.yAl.sub.zGa.sub.(1-y-z)N (0<y1, 0z<1, y+z1). The second nitride region includes a sixth partial region. The third nitride region includes Al.sub.x3Ga.sub.1-x3N (x1<x3<x2). The third nitride region includes a seventh partial region.

Disclosed are a semiconductor comprising amorphous tellurium oxide, thin film transistor and method of fabricating same. In detail, a semiconductor comprising a chalcogen atom comprising at least one selected from the group consisting of a sulfur atom (S) and a selenium atom (Se); and tellurium composite comprising a tellurium (Te) atom and tellurium oxide. A thin film transistor (TFT) fabricated based on the TeO.sub.x channel layer according to the present disclosure exhibits excellent output/transfer characteristics and superior electrical performance with high hole field-effect mobility and a high on/off current ratio of 10.sup.7.

A method of fabricating a semiconductor device includes providing a substrate, implementing a growth procedure to form a semiconductor layer supported by the substrate, performing an anneal of the semiconductor layer, the anneal being conducted at a higher temperature than the growth procedure, and repeating the growth procedure and the anneal. The anneal is conducted at or above a decomposition temperature for the semiconductor layer.

A method includes forming a first masking layer over a substrate, the first masking layer including a first mask line and a second mask line, heating respective top surfaces of the first mask line and the second mask line with polarized light, and forming a second masking layer over the first masking layer with an area selective deposition process. The second masking layer is thinner over a sidewall of the first mask line than over a top surface of the first mask line.

A Low Pressure Chemical Vapor Deposition (LPCVD) technique is provided to produce improved dielectric/semiconductor interfaces for GaN-based electronic devices. Using the LPCVD technique, superior interfaces are achieved through the use of elevated deposition temperatures (>700 C.), the use of ammonia to stabilize and clean the GaN surface, and chlorine-containing precursors where reactions with chlorine remove unwanted impurities from the dielectric film and its interface with GaN. The LPCVD silicon nitride films have less hydrogen contamination, higher density, lower buffered-HF etch rates, and lower pin hole density than films produced by other deposition techniques making the LPCVD coatings suitable for device passivation. A metal insulator semiconductor (MIS) structures fabricated with LPCVD SiN on GaN exhibit near ideal capacitance-voltage behavior with both charge accumulation, depletion, and inversion regimes.

A method includes removing a first dummy gate structure to form a recess around a first nanostructure and a second nanostructure; depositing a sacrificial layer in the recess with a flowable chemical vapor deposition (CVD); and patterning the sacrificial layer to leave a portion of the sacrificial layer between the first nanostructure and the second nanostructure. The method further include depositing a first work function metal in first recess; removing the first work function metal and the portion of the sacrificial layer from the recess; depositing a second work function metal in the recess, wherein the second work function metal is of an opposite type than the first work function metal; and depositing a fill metal over the second work function metal in the recess.