A chip package comprises an interposer; an FPGA IC chip over the interposer, wherein the FPGA IC chip comprises a programmable logic block configured to perform a logic operation on its inputs, wherein the programmable logic block comprises a look-up table configured to be provided with multiple resulting values of the logic operation on multiple combinations of the inputs of the programmable logic block respectively, wherein the programmable logic block is configured to select, in accordance with one of the combinations of its inputs, one from the resulting values into its output, and multiple non-volatile memory cells configured to save the resulting values respectively; multiple first metal bumps between the interposer and the FPGA IC chip; and an underfill between the interposer and the FPGA IC chip, wherein the underfill encloses the first metal bumps.

A packaging structure for a light emitter pixel array includes a plurality of pixels, with at least some pixels laterally separated from each other with a pixel light confinement structure. An inorganic substrate having a top redistribution layer is attached to the plurality of pixels and at least one through silicon via containing an electrical conductor is defined to pass through the inorganic substrate and support an electrical coupling with the top redistribution layer.

A method of forming one or more semiconductor packages includes mounting one or more semiconductor dies on the metal strip such that the one or more semiconductor dies are in a flip chip arrangement whereby terminals of the one or more semiconductor dies face the upper surface of the metal strip, forming an electrically insulating encapsulant material on the upper surface of the metal strip that encapsulates the one or more semiconductor dies, and forming package terminals that are electrically connected with the terminals of the one or more semiconductor dies, wherein the package terminals are formed from the metal strip or from metal that is deposited after removing the metal strip.

Embodiments disclosed herein include electronic packages and methods of forming such electronic packages. In an embodiment, an electronic package comprises a plurality of stacked layers. In an embodiment, a first trace is on a first layer, wherein the first trace has a first thickness. In an embodiment, a second trace is on the first layer, wherein the second trace has a second thickness that is greater than the first thickness. In an embodiment, a second layer is over the first trace and the second trace.

A semiconductor device structure is provided. The semiconductor device structure includes an interconnection structure over a semiconductor substrate and a conductive pillar over the interconnection structure. The conductive pillar has a protruding portion extending towards the semiconductor substrate from a lower surface of the conductive pillar. The semiconductor device structure also includes an upper conductive via between the conductive pillar and the interconnection structure and a lower conductive via between the upper conductive via and the interconnection structure. The lower conductive via is electrically connected to the conductive pillar through the upper conductive via. The conductive pillar extends across opposite sidewalls of the upper conductive via and opposite sidewalls of the lower conductive via. A top view of an entirety of the second conductive via is separated from a top view of an entirety of the protruding portion.

A method includes forming a seed layer on a substrate. The seed layer includes a first metal. The method also includes forming a first metal layer over the seed layer. The first metal layer includes a second metal. The method further includes forming a second metal layer over the first metal layer. The second metal layer includes the first metal. The method includes converting at least a portion of the first metal layer into an alloy of the first metal and the second metal. The seed layer is then etched.

A semiconductor package includes a first substrate including upper pads, at least one chip structure including connection pads, and first bump structures electrically connecting the connection pads and the upper pads. The connection pads include a first group of connection pads arranged at a first interval, and a second group of connection pads arranged at a second interval, smaller than the first interval. Each of the first group of the first bump structures includes a first pillar contacting one of the first group of the connection pads, and a first solder connecting the first pillar and one of the upper pads. Each of the second group of the first bump structures includes a second pillar contacting one of the second group of the connection pads, a second solder contacting one of the upper pads, and a third pillar connecting the second pillar and the second solder.

Provided is a semiconductor package with improvement in warpage thereof and a method of fabricating the semiconductor package. The semiconductor package includes a first semiconductor chip, a redistribution substrate on the first semiconductor chip, a second semiconductor chip on the redistribution substrate, a first encapsulant encapsulating the second semiconductor chip, on the redistribution substrate, a metal post arranged on a top surface of the first semiconductor chip, and a second encapsulant covering side surfaces of the metal post, on the bottom surface of the first semiconductor chip.

A method includes: providing a support substrate covered by a separation layer, a seed layer, a resin layer having openings; forming, through the openings, interconnection elements by depositing a solder layer, a copper pillar, and optionally a gold layer; removing the resin, and etching the non-covered portion of the seed layer; assembling the interconnection elements to an assembly comprising a substrate in which are formed first chips and second chips assembled to the first chips; wherein the interconnection elements are assembled by thermocompression onto conductive landing areas positioned on the substrate coupled to the first chips; and removing the temporary support and the separation layer.

A method includes providing an interposer structure including conductive paths, forming micro bumps over the interposer structure and connected to the conductive paths, bonding a first die and a second die onto the micro bumps, forming a molding compound over and around the first die and the second die, performing a planarization process to expose a top surface of the second die, forming a trench in the molding compound to expose a top surface of the first die, forming a thermal interface material (TIM) layer in the trench and over the top surface of the second die, bonding the interposer structure to a substrate, and attaching a heat sink onto the TIM layer. The first die has a first height and the second die has a second height greater than the first height.