The present invention discloses an elastic heat spreader for chip packaging, a packaging structure and a packaging method. The heat spreader includes a top cover plate and a side cover plate that extends outward along an edge of the top cover plate, wherein the top cover plate is configured to be placed on a chip, and at least a partial region of the side cover plate is an elastic member; and the elastic member at least enables the side cover plate to be telescopic in a direction perpendicular to the top cover plate. According to the present invention, a following problem is solved: delamination between the heat spreader and a substrate as well as the chip due to stress generated by different thermal expansion coefficients of the substrate, the heat spreader and the chip in a packaging process of a large-size product.

A method of manufacturing a semiconductor device includes: adhering together a heat generating body and a heat dissipating body via a thermally conductive sheet by applying a pressure on the heat generating body and the heat dissipating body in a thickness direction of the thermally conductive sheet with the thermally conductive sheet disposed therebetween, the thermally conductive sheet having a compression modulus of 1.40 MPa or less under a compressive stress of 0.10 MPa at 150 C., and a tack strength of 5.0 N.Math.mm or more at 25 C.

A temperature regulation unit (10) includes a plurality of stacked porous metal structures (for example, metal fiber structures (40, 42)) each of which has a plurality of rod-shaped members (32, 34) extending parallel to each other so as to be spaced apart from each other and a connection member (24, 26) connecting the respective rod-shaped members (32, 34) and is formed from metal, the respective rod-shaped members (32, 34) of the respective porous metal structures extend parallel to each other, and a flow passage (50) for a fluid is formed in a gap between the respective rod-shaped members (32, 34).

This copper/ceramic assembly includes: a copper member consisting of copper or a copper alloy; and a ceramic member, wherein the copper member and the ceramic member are bonded to each other. At a bonded interface between the ceramic member and the copper member, an active metal compound layer is formed on a side of the ceramic member. In a region extending by 10 m from the active metal compound layer toward a side of the copper member, an area rate of an active metal carbide is 8% or less.

A semiconductor device has a joint part in which a first conducting part and a second conducting part are joined by a joint material. The first conducting part has a high wettability region and a low wettability region in a surface opposite to the second conducting part. The low wettability region is adjacent to the high wettability region to define an outer periphery of the high wettability region and has wettability lower than the high wettability region to the joint material. The high wettability region has an overlap region overlapping a formation region of the joint part in the second conducting part in a planar view, and a non-overlap region connected to the overlap region and not overlapping the formation region of the joint part in the second conducting part. The non-overlap region includes a holding region capable of holding the joint material that is surplus for the joint part.

An electronic device is provided. An example electronic device includes: a semiconductor body of Silicon Carbide, having a surface having a first portion of the surface that defines an active region of the electronic device and a second portion of the surface that is external to the active region; a metallization extending on the first portion of the surface of the semiconductor body; a passivation layer extending on part of the metallization; and an adhesion layer, based on one or more carbon allotropes, extending on the passivation layer.

A solid state drive (SSD) includes a case including a planar portion, a protrusion portion protruding from the planar portion, and a plurality of fins protruding from the planar portion and defining an internal space, a printed circuit board located within the internal space of the case and including a semiconductor device and a controller, and a heat dissipation sheet covering the planar portion and the protrusion portion of the case. The plurality of fins are spaced apart from the protrusion portion and the printed circuit board in a first direction, an upper surface of the semiconductor device and an upper surface of the controller are in direct contact with the heat dissipation sheet, and the heat dissipation sheet includes at least one of graphite, graphene, carbon nanotubes, and fullerene.

An electronic device includes a substrate having conductive features, and a semiconductor die having conductive terminals along a first side, and an indent that extends into an opposite second side, the conductive terminals attached to respective ones of the conductive features of the substrate. A method of fabricating an electronic device includes forming an indent into a second side of a semiconductor die and attaching conductive terminals along an opposite first side of the semiconductor die to respective conductive features of a substrate.

A package structure includes a package substrate, a package module on the package substrate, an outer molding material layer on the package substrate around the package module, a thermal interface material (TIM) layer on the package module, and a package lid on the TIM layer and attached to the outer molding material layer. The package lid includes a bottom lid portion having a first coefficient of thermal expansion (CTE), and a top lid portion attached to the bottom lid portion and having a second CTE less than the first CTE.

A device structure includes a voltage regulator circuit, which includes: a first semiconductor die including a pulse width modulation (PWM) circuit and connected to a PWM voltage output node at which a pulsed voltage output is generated; and a series connection of an inductor and a parallel connection circuit, the parallel connection circuit including a parallel connection of capacitor-switch assemblies. A first end node of the series connection is connected to the PWM voltage output node; a second end node of the series connection is connected to electrical ground; each of the capacitor-switch assemblies includes a respective series connection of a respective capacitor and a respective switch; and each switch within the capacitor-switch assemblies is located within the first semiconductor die.