A semiconductor arrangement is disclosed. The semiconductor arrangement includes a semiconductor layer having a first surface; a buried region of a first doping type formed in the semiconductor layer spaced apart from the first surface; an isolating grid extending from the first surface to the buried region and including a first region of the first doping type; and device regions of the second doping type adjoining the buried region and isolated from each other by the isolating grid.

In a method of manufacturing a semiconductor device, a first-conductivity type implantation region is formed in a semiconductor substrate, and a carbon implantation region is formed at a side boundary region of the first-conductivity type implantation region.

A semiconductor structure and method for manufacturing thereof are provided. The semiconductor structure includes a silicon substrate having a first surface, a III-V layer on the first surface of the silicon substrate and over a first active region, and an isolation region in a portion of the III-V layer extended beyond the first active region. The first active region is in proximal to the first surface. The method includes the following operations. A silicon substrate having a first device region and a second device region is provided, a first active region is defined in the first device region, a III-V layer is formed on the silicon substrate, an isolation region is defined across a material interface in the III-V layer by an implantation operation, and an interconnect penetrating through the isolation region is formed.

A nitride-based semiconductor circuit including a first semiconductor substrate, a second semiconductor substrate, a nitride-based heterostructure, connectors, a first patterned conductive layer, a second patterned conductive layer, and connecting vias is provided. The second substrate is disposed on the first substrate. The first substrate has first dopants, and the second substrate has second dopants, which is different from the first dopants, and a pn junction is formed between the first substrate and the second substrate. The nitride-based heterostructure is disposed on the second substrate. The connectors are disposed on the nitride-based heterostructure. The first and second patterned conductive layers are disposed on the connectors. The connecting vias include a first interconnection and a second interconnection. The first interconnection electrically connects the first substrate to one of the connectors. The second interconnection electrically connects the second substrate to another one of the connectors.

Group III oxide semiconducting devices with effective device isolation and edge termination regions.

A transistor device includes: a semiconductor substrate having a doping concentration of a first dopant type; a highly doped source region of a second dopant type formed in a first surface of the semiconductor substrate; a first highly doped drain region of the second dopant type formed in the first surface; a gate structure arranged on the first surface and including a gate electrode formed on the first surface; and a first lightly doped region formed in the first surface and extending from the highly doped source region under the gate electrode. A channel region extends between the first lightly doped region and the highly doped drain region. The channel region has an average doping level of the first dopant type of n10.sup.x that varies by less than 0.5n10.sup.X between the first lightly doped region and the highly doped drain region along the lateral direction parallel to the first surface.

The present disclosure relates to semiconductor structures and, more particularly, to built-in temperature sensors and methods of manufacture and operation. The structure includes: a semiconductor on insulator substrate; an insulator layer under the semiconductor on the insulator substrate; a handle substrate under insulator layer; a first well of a first dopant type in the handle substrate; a second well of a second dopant type in the handle substrate, adjacent to the first well; and a back-gate diode at a juncture of the first well and the second well.

A circuit device includes core circuitry. The circuit device further includes a first plurality of guard rings having a first dopant type, wherein the first plurality of guard rings is around a periphery of the core circuitry. The circuit device further includes a second plurality of guard rings having a second dopant type, wherein the second dopant type is opposite to the first dopant type, and at least one guard ring of the second plurality of guard rings is around a periphery of at least one guard ring of the first plurality of guard rings. Guard rings of the first plurality of guard rings are in a concentric arrangement.

There is provided a diode including an anode electrode provided on a side of a front surface of a semiconductor substrate, an interlayer dielectric film disposed between the semiconductor substrate and the anode electrode, a first anode region of a first conductivity type provided on the front surface of the semiconductor substrate, a second anode region of a second conductivity type, which is different from the first conductivity type, provided on the front surface of the semiconductor substrate, a first contact hole provided in the interlayer dielectric film, causing the anode electrode to be in Schottky contact with the first anode region, and a second contact hole provided in the interlayer dielectric film and different from the first contact hole, causing the anode electrode to be in ohmic contact with the second anode region.

A semiconductor device is provided. The semiconductor device includes a first semiconductive region, a second semiconductive region, an isolation structure and at least one inner insulating via. The isolation structure is formed between the first semiconductive region and the second semiconductive region and includes an isolation bottom formed beneath the second semiconductive region and an isolation ring. The isolation ring includes a plurality of insulating regions and a plurality of doped regions formed alternately. The isolation bottom and the plurality of insulating regions have insulating materials. The plurality of doped regions have dopants of a conductivity type complementary to those of the first and second semiconductive regions. The isolation ring has a lower portion connecting the isolation bottom and an upper portion surrounding the second semiconductive region. The inner insulating via is formed in the second semiconductive region, on the isolation bottom and surrounded by the isolation ring.