A transistor having a minute size is provided. The transistor includes a first conductive layer, a second conductive layer, a third conductive layer, a first insulating layer, a second insulating layer, and a semiconductor layer. The first insulating layer is provided over the first conductive layer and includes an opening reaching the first conductive layer and a depressed portion surrounding the opening in a plan view. The second conductive layer is provided to cover the inner wall of the depressed portion and includes a region facing the semiconductor layer with the first insulating layer therebetween. The semiconductor layer is provided to include a region overlapping with the opening and is in contact with the top surface of the first conductive layer, the side surface of the first insulating layer, the side surface of the second conductive layer, and the top surface of the second conductive layer. The second insulating layer is provided in contact with the top surface of the semiconductor layer. The third conductive layer is provided over the second insulating layer to cover the inner wall of the opening and includes a region facing the semiconductor layer with the second insulating layer therebetween.

The present invention addresses the problem of providing a novel SiC epitaxial substrate manufacturing method and manufacturing device therefor. An SiC substrate and an SiC material, which has a lower doping concentration than said SiC substrate, are heated facing one another, and material is transported from the SiC material to the SiC substrate to form an SiC epitaxial layer. As a result, in comparison with the existing method (chemical vapour deposition), it is possible to provide an SiC epitaxial substrate manufacturing method with a reduced number of parameters to be controlled.

A process for producing semiconductor structures comprising one of more layers of Group III/IV Compounds deposited onto a template using PVD sputtering the resulting semiconductor structures is provided according to the invention. The Group III or Group IV material may be gallium, hafnium, indium, aluminum, silicon, germanium, magnesium and/or zirconium. The anion provided by a reactive gas may be nitride, oxide, arsenide, or phosphide. The flow of the reactive gas to the vacuum chamber used to react with the sputtered Group III or Group IV target material for produce the Group III/IV Compound layer onto the template is modulated during a duty cycle during the PVD sputtering process between a target-rich condition and a reactive gas-rich condition to enhance the efficiency of the PVD sputtering process and improve the crystallinity of the Group III/IV Compound layer within the resulting semiconductor structure.

A crystalline IZTO oxide semiconductor and a thin film transistor having the same are provided. The thin film transistor includes a gate electrode, a crystalline InZnSn oxide (IZTO) channel layer overlapping the upper or lower portions of the gate electrode and having hexagonal crystal grains, and a gate insulating layer disposed between the gate electrode and the IZTO channel layer, and source and drain electrodes respectively connected to both ends of the IZTO channel layer.

Utility of an ECR plasma technique is enhanced. A film forming apparatus 1 deposits, on a surface of a substrate SUB, first target particles emitted by bombardment of ions (ions making ECR plasma) with a cylindrical target TA mounted on a cylindrical-target mounting section 27 and second target particles emitted by bombardment of ions (ions making plasma which is different in density from the ECR plasma) with a disk target TA2 mounted on a disk-target mounting section 31.

A semiconductor device with a small variation in transistor characteristics is provided. The semiconductor device includes an oxide semiconductor film, a source electrode and a drain electrode over the oxide semiconductor film, an interlayer insulating film placed to cover the oxide semiconductor film, the source electrode, and the drain electrode, a first gate insulating film over the oxide semiconductor film, a second gate insulating film over the first gate insulating film, and a gate electrode over the second gate insulating film. The interlayer insulating film has an opening overlapping with a region between the source electrode and the drain electrode, the first gate insulating film, the second gate insulating film, and the gate electrode are placed in the opening of the interlayer insulating film, the first gate insulating film includes oxygen and aluminum, and the first gate insulating film includes a region thinner that is than the second gate insulating film.

Provided are a crack-free laminated film and a structure including this laminated film. This laminated film includes: a buffer layer; and at least one layer of gallium nitride base film disposed on the buffer layer. Moreover, the compression stress of the entire laminated film is 2.0 to 5.0 GPa.

A preparation method of an aluminum nitride (AlN) composite structure based on a two-dimensional (2D) crystal transition layer is provided. The preparation method includes: transferring the 2D crystal transition layer on a first periodic groove of an epitaxial substrate; forming a second periodic groove staggered with the first periodic groove on the 2D crystal transition layer; depositing a supporting protective layer; depositing a functional layer of a required AlN-based material; and removing the 2D crystal transition layer through thermal oxidation to obtain a semi-suspended AlN composite structure. The preparation method has low difficulty and is suitable for large-scale industrial production. Design windows of the periodic grooves and the AlN functional layer are large and can meet the material requirements of deep ultraviolet light-emitting diodes (DUV-LEDs) and radio frequency (RF) electronic devices for different purposes, resulting in a wide application range.

A Schottky barrier diode, including a first n-type semiconductor layer including a -Ga.sub.2O.sub.3-based single crystal epitaxial layer and having a first carrier concentration that determines reverse breakdown voltage and forward voltage, a second n-type semiconductor layer including a -Ga.sub.2O.sub.3-based single crystal substrate and having a second carrier concentration that is higher than the first carrier concentration and determines forward voltage, a Schottky electrode provided on a surface of the first n-type semiconductor layer on the opposite side to the second n-type semiconductor layer, and an ohmic electrode provided on a surface of the second n-type semiconductor layer on the opposite side to the first n-type semiconductor layer. The -Ga.sub.2O.sub.3-based single crystal substrate includes a surface that has a plane orientation rotated by an angle of not more than 37.5 from a (010) plane.

Provided are high quality metal-nitride, such as aluminum nitride (AlN), films for heat dissipation and heat spreading applications, methods of preparing the same, and deposition of high thermal conductivity heat spreading layers for use in RF devices such as power amplifiers, high electron mobility transistors, etc. Aspects of the inventive concept can be used to enable heterogeneously integrated compound semiconductor on silicon devices or can be used in in non-RF applications as the power densities of these highly scaled microelectronic devices continues to increase.