A method for manufacturing a gallium nitride film includes the steps of placing a substrate so as to face a target containing nitrogen and gallium in a vacuum chamber, supplying a sputtering gas into the vacuum chamber, supplying a nitrogen radical into the vacuum chamber, generating a plasma of the sputtering gas by application of a voltage to the target, generating a gallium ion by a collision of an ion of the sputtering gas with the target, and stopping the application of the voltage to the target and depositing gallium nitride on the substrate. The gallium nitride is generated by a reaction of the gallium ion with a nitrogen anion which is generated by a reaction of an electron in the vacuum chamber with the nitrogen radical.

Disclosed are an MPS diode device and a preparation method therefor. The MPS diode device comprises a plurality of cells arranged in parallel, wherein each cell comprises a cathode electrode, and a substrate, epitaxial layer, buffer layer, and anode electrode that are formed in succession on the cathode electrode; two active regions are formed on the side of the epitaxial layer away from the substrate; the width of forbidden band of the buffer layer is greater than the width of forbidden band of the epitaxial layer, and a material of the buffer layer and a material of the epitaxial layer are allotropes; and first openings are formed at the positions in the buffer layer opposite to the active regions, and an ohmic metal layer is formed in the first openings.

Disclosed are a semiconductor comprising amorphous tellurium oxide, thin film transistor and method of fabricating same. In detail, a semiconductor comprising a chalcogen atom comprising at least one selected from the group consisting of a sulfur atom (S) and a selenium atom (Se); and tellurium composite comprising a tellurium (Te) atom and tellurium oxide. A thin film transistor (TFT) fabricated based on the TeO.sub.x channel layer according to the present disclosure exhibits excellent output/transfer characteristics and superior electrical performance with high hole field-effect mobility and a high on/off current ratio of 10.sup.7.

A method of fabricating a semiconductor device includes providing a substrate, implementing a growth procedure to form a semiconductor layer supported by the substrate, performing an anneal of the semiconductor layer, the anneal being conducted at a higher temperature than the growth procedure, and repeating the growth procedure and the anneal. The anneal is conducted at or above a decomposition temperature for the semiconductor layer.

A method of fabricating a semiconductor device includes providing a substrate, implementing a growth procedure to form a semiconductor layer supported by the substrate, performing an anneal of the semiconductor layer, the anneal being conducted at a higher temperature than the growth procedure, and repeating the growth procedure and the anneal. The anneal is conducted at or above a decomposition temperature for the semiconductor layer.

A method for manufacturing a semiconductor device with high productivity is provided. The method includes a step of forming a first insulator, a second insulator, and a third insulator in this order using a multi-chamber apparatus; a step of forming a fourth insulator, a fifth insulator, a first oxide film, a second oxide film, and a third oxide film in this order using a multi-chamber apparatus; a step of forming a conductive film; a step of processing the first oxide film, the second oxide film, the third oxide film, and the conductive film, thereby forming a first oxide, a second oxide, an oxide layer, and a conductive layer each having an island shape; a step of forming a sixth insulator and an insulating film in this order using a multi-chamber apparatus; a step of planarizing the insulating film; a step of forming, in the insulating film and the sixth insulator, an opening where the second oxide is exposed; a step of forming a seventh insulator and a first conductor; and a step of forming an eighth insulator and a ninth insulator in this order using a multi-chamber apparatus.

A method of fabricating semiconducting tellurium (Te) nanomesh. The method includes the steps of preparing a substrate, vaporizing Te powders under a first temperature; and growing Te nanomesh on the substrate using the vaporized Te powders under a second temperature. The first temperature is higher than the second temperature. The rationally designed nanomesh exhibits exciting properties, such as micrometer-level patterning capacity, excellent field-effect hole mobility, fast photoresponse in the optical communication region, and controllable electronic structure of the mixed-dimensional heterojunctions.

An object of the present invention is to provide a novel technique capable of suppressing the occurrence of cracks in the growth layer. The present invention is a method for manufacturing a semiconductor substrate, which includes: an embrittlement processing step S10 of reducing strength of an underlying substrate 10; and a crystal growth step S20 of forming the growth layer 20 on the underlying substrate 10. In addition, the present invention is a method for suppressing the occurrence of cracks in the growth layer 20, and this method includes an embrittlement processing step S10 of reducing the strength of the underlying substrate 10 before forming the growth layer 20 on the underlying substrate 10.

Inorganic semiconductors typically have limited p-type behavior due to the scarcity of holes and the localized valence band maximum, hindering the progress of complementary devices and circuits. In this work, we propose an inorganic blending strategy to activate the hole-transporting character in an inorganic semiconductor compound, namely tellurium-selenium-oxygen (TeSeO). By rationally combining intrinsic p-type semimetal, semiconductor, and wide-bandgap semiconductor into a single compound, the TeSeO system displays tunable bandgaps ranging from 0.7 to 2.2 eV. Wafer-scale ultrathin TeSeO films, which can be deposited at room temperature, display high hole field-effect mobility of 48.5 cm.sup.2/(Vs) and robust hole transport properties, facilitated by TeTe (Se) portions and OTeO portions, respectively.

Embodiments of the disclosure relate to methods of selectively depositing polysilicon after forming a flowable polymer film to protect a substrate surface within a feature. A first silicon (Si) layer is deposited by physical vapor deposition (PVD). The flowable polymer film is formed on the first silicon (Si) layer on the bottom. A portion of the first silicon (Si) layer is selectively removed from the top surface and the at least one sidewall. The flowable polymer film is removed. In some embodiments, a second silicon (Si) layer is selectively deposited on the first silicon (Si) layer to fill the feature. In some embodiments, the remaining portion of the first silicon (Si) layer on the bottom is oxidized to form a first silicon oxide (SiOx) layer on the bottom, and a silicon (Si) layer or a second silicon oxide (SiOx) layer is deposited on the first silicon oxide (SiOx) layer.