A method for manufacturing a silicon substrate for a quantum computer, the method includes the steps of forming a Si epitaxial layer by epitaxial growth using a Si source gas as a silicon-based raw material gas, in which a total content of 28Si and 30Si in a whole silicon contained in the silicon-based raw material gas is 99.9% or more, on a silicon substrate, forming an oxygen (O) -doped layer by oxidizing a surface of the Si epitaxial layer, and forming a Si epitaxial layer by epitaxial growth using a Si source gas, in which a total content of 28Si and 30Si in a whole silicon contained in the silicon-based raw material gas is 99.9% or more, on the -doped layer.

The present invention provides a semiconductor structure comprising: a silicon substrate in [100] orientation; a scandium oxide layer over the substrate, in [111] orientation; and a scandium-rare earth-oxide layer over the scandium oxide layer. The scandium-rare earth-oxide layer can have a graded composition to transition lattice constant to match to a subsequent layer, such as an indium nitride layer having very high electron drift velocity. InN over Si (100) offers transistors, photonics and passive electronics that operate in the terahertz frequency range.

An IGZO thin-film transistor and a method for manufacturing same. The method includes: acquiring a substrate; forming an IGZO layer on the substrate by a solution process; doping V impurities on a surface of the IGZO layer by a spin doping process; forming a source electrode at one side of the IGZO layer, and forming a drain electrode at the other side; forming a gate dielectric layer on the doped IGZO layer; and forming a gate electrode on the gate dielectric layer.

Disclosed are a semiconductor comprising amorphous tellurium oxide, thin film transistor and method of fabricating same. In detail, a semiconductor comprising a chalcogen atom comprising at least one selected from the group consisting of a sulfur atom (S) and a selenium atom (Se); and tellurium composite comprising a tellurium (Te) atom and tellurium oxide. A thin film transistor (TFT) fabricated based on the TeO.sub.x channel layer according to the present disclosure exhibits excellent output/transfer characteristics and superior electrical performance with high hole field-effect mobility and a high on/off current ratio of 10.sup.7.

In a first step S101, a first region in which a polarity inversion layer is formed, and a second region in which the polarity inversion layer is not formed are provided on a substrate. Next, in a second step S102, a first nitride semiconductor is epitaxially grown on the substrate having the first region and the second region along the c-axis direction such that a first semiconductor layer is formed. Next, in a third step S103, a second nitride semiconductor is epitaxially grown on the first semiconductor layer along the c-axis direction such that a second semiconductor layer is formed on the first semiconductor layer. The second nitride semiconductor has different polarization, electron affinity, and band-gap energy from the first nitride semiconductor. The second semiconductor layer forms a heterojunction with the first semiconductor layer. The interface therebetween has a polarization charge, which is positive or negative depending on polarity.

A method of forming conductive member includes: forming, on substrate, first portion containing first element constituting the conductive member to be obtained and second element causing eutectic reaction with the first element, and second portion containing third element constituting intermetallic compound with the second element; crystallizing primary crystals of the first element by adjusting temperature of the substrate after bringing the first portion into liquid phase state; growing crystal grains of the first element by diffusing the second element from the first portion into the second portion to increase ratio of the first element in crystal state to the first and second elements in the liquid phase state in the first portion while maintaining the temperature of the substrate at the same temperature; and turning the first portion, after completing diffusion of the second element into the second portion, into the conductive member having crystal grains of the first element.

A wafer includes a buried substrate; a layer of silicon (100) disposed on the buried substrate and forming multiple U-shaped grooves, wherein each U-shaped groove comprises a bottom portion and silicon sidewalls (111) at an angle to the buried substrate; a buffer layer disposed within the multiple U-shaped grooves; and multiple gallium nitride (GaN)-based structures having vertical sidewalls disposed within and protruding above the multiple U-shaped grooves, the multiple GaN-based structures each including cubic gallium nitride (c-GaN) formed at merged growth fronts of hexagonal gallium nitride (h-GaN) that extend from the silicon sidewalls (111).

A semiconductor-on-insulator substrate for use in RF applications, such as a silicon-on-insulator substrate, comprises a semiconductor top layer, a buried oxide layer and a passivation layer over a support substrate. In addition, a penetration layer is provided between the passivation layer and the silicon support substrate to ensure sufficient high resistivity below RF features and avoid increased migration of dislocations in the support substrate. RF devices may be fabricated on and/or in such a semiconductor-on-insulator substrate.

In a described example, an integrated circuit (IC) is disclosed that includes a transistor. The transistor includes a substrate, and a buffer structure overlying the substrate. The buffer structure has a first buffer layer, a second buffer layer overlying the first buffer layer, and a third buffer layer overlying the second buffer layer. The first buffer layer has a first carbon concentration, the second buffer layer has a second carbon concentration lower than the first carbon concentration, and the third buffer layer has a third carbon concentration higher than the second carbon concentration. An active structure overlies the buffer structure.

A substrate processing method of processing a substrate having a base film includes a loading process of loading the substrate into a processing container, a first process of performing a first plasma process in a state where the loaded substrate is held at a first position by raising substrate support pins of a stage arranged in the processing container, and a second process of performing a second plasma process while holding the substrate at a second position by lowering the substrate support pins.