According to one embodiment, a semiconductor manufacturing apparatus includes a chamber that is used for deposition of an oxide film, a susceptor that is provided in the chamber and on which a substrate is placed, at least a supply pipe that supplies a gas to the chamber, an exhaust pipe that exhausts the gas from the chamber, and a controller that is configured to control supply of each of a first source gas, an oxidizing gas, a reducing gas activated by plasma, and a first halide gas activated by plasma to the chamber, and gas exhaust from the chamber.

A transistor may be provided by forming, in a forward order or in a reverse order, a gate electrode, a semiconducting metal oxide liner, a gate dielectric, and an active layer over a substrate, and by forming a source electrode and a drain electrode on end portions of the active layer. The semiconducting metal oxide liner comprises a thin semiconducting metal oxide material that functions as a hydrogen barrier material.

A first thin film transistor and a second thin film transistor include a semiconducting metal oxide plate located over a substrate, and a set of electrode structures located on the semiconducting metal oxide plate and comprising, from one side to another, a first source electrode, a first gate electrode, a drain electrode, a second gate electrode, and a second source electrode. A bit line is electrically connected to the drain electrode, and laterally extends along a horizontal direction. A first capacitor structure includes a first conductive node that is electrically connected to the first source electrode. A second capacitor structure includes a second conductive node that is electrically connected to the second source electrode.

A semiconductor device includes an oxide semiconductor stack, a first gate, a first contact structure, and a second contact structure. The oxide semiconductor stack includes an n-type oxide semiconductor layer and a p-type oxide semiconductor layer stacked on each other. The first gate is over the oxide semiconductor stack. The first contact structure and the second contact structure are at opposite sides of the first gate and electrically connected to the oxide semiconductor stack.

As a display device has a higher definition, the number of pixels, gate lines, and signal lines are increased. When the number of the gate lines and the signal lines are increased, a problem of higher manufacturing cost, because it is difficult to mount an IC chip including a driver circuit for driving of the gate and signal lines by bonding or the like. A pixel portion and a driver circuit for driving the pixel portion are provided over the same substrate, and at least part of the driver circuit includes a thin film transistor using an oxide semiconductor interposed between gate electrodes provided above and below the oxide semiconductor. Therefore, when the pixel portion and the driver portion are provided over the same substrate, manufacturing cost can be reduced.

Methods for selective deposition are provided. Material is selectively deposited on a first surface of a substrate relative to a second surface of a different material composition. An inhibitor, such as a polyimide layer, is selectively formed from vapor phase reactants on the first surface relative to the second surface. A layer of interest is selectively deposited from vapor phase reactants on the second surface relative to the first surface. The first surface can be metallic while the second surface is dielectric. Accordingly, material, such as a dielectric transition metal oxides and nitrides, can be selectively deposited on metallic surfaces relative dielectric surfaces using techniques described herein.

A semiconductor device includes a substrate, and a first transistor disposed on the substrate. The first transistor includes a first channel layer, a magnesium oxide layer, a first gate electrode, a first gate dielectric and first source/drain electrodes. A crystal orientation of the first channel layer is <100> or <110>. The magnesium oxide layer is located below the first channel layer and in contact with the first channel layer. The first gate electrode is located over the first channel layer. The first gate dielectric is located in between the first channel layer and the first gate electrode. The first source/drain electrodes are disposed on the first channel layer.

A method for forming a film, including: atomizing a raw material solution into a mist to form raw material mist; mixing raw material mist and a carrier gas to form gas mixture; placing a substrate on a placement section of susceptor; supplying gas mixture from an atomizer to the substrate to perform film formation by thermal reaction on substrate; and discharging gas mixture after the film formation through an exhaust unit, wherein in the step of supplying the gas mixture from atomizer to substrate to perform film formation by thermal reaction on the substrate, at least a part of gas mixture is supplied from a smooth section adjacent to placement section to a surface of substrate, the smooth section having a surface roughness of 200 m or less. A method for forming a film capable of uniformly and stably producing a high-quality film on a surface of a large-diameter substrate.

A method of forming a semiconductor structure includes forming a photoresist pattern on an anti-reflective layer on a wafer; forming an oxide layer on the anti-reflective layer and the photoresist pattern, wherein the oxide layer has a protruding portion overlapping the photoresist pattern; forming a polish stop layer along a top surface of the oxide layer; forming a buffer layer on the polish stop layer; polishing the buffer layer such that at least a portion of the buffer layer is removed and the polish stop layer is exposed; and etching the buffer layer, the polish stop layer and the oxide layer such that the photoresist pattern is exposed.

Disclosed herein are compositions, methods, and devices. Disclosed herein is a composition comprising a -(Al.sub.xGa.sub.1-x).sub.2O.sub.3, having an x value of less than about 5% and comprising at least one n-carrier dopant. Also disclosed are methods of making the same. Also disclosed are devices comprising the disclosed compositions.