In an embodiment, a device includes: a first fin extending from a substrate; a gate stack disposed on the first fin; a source/drain region disposed in the first fin; a contact etch stop layer (CESL) disposed over the source/drain region; a gate spacer extending along a side of the gate stack; and a dielectric plug disposed between the CESL and the gate spacer, where the dielectric plug, the CESL, the gate spacer, and the source/drain region collectively define a void physically separating the gate stack from the source/drain region.

An apparatus includes a processing chamber, a substrate support in the processing chamber, a plasma source coupled to the processing chamber, and a plurality of heating devices arranged on the processing chamber. Each heating device is configured to emit laser beam on a substrate positioned on the substrate support to heat the substrate.

A technique improves etch selectivity. An etching includes (a) providing, in a chamber, a substrate including an underlying film and a silicon-containing film on the underlying film, (b) etching the silicon-containing film to form a recess with first plasma generated from a first process gas containing a hydrogen fluoride gas until before the underlying film is exposed at the recess or until the underlying film is partly exposed at the recess, and (c) further etching the silicon-containing film at the recess under a condition different from a condition of (b).

Disclosed are a semiconductor structure and a method for manufacturing a semiconductor structure, the method includes: forming a first transition layer, a protection layer and an active structure layer sequentially epitaxially on a side of a growth substrate, where a surface, away from the growth substrate, of the first transition layer is a two-dimensional flat surface; on a first plane, an orthographic projection of the active structure layer is at least partially covered by an orthographic projection of the protection layer, and the first plane is perpendicular to an arrangement direction of the protection layer and the active structure layer; detaching the growth substrate by a laser lift-off process, to make the epitaxial layer transferred to a transfer substrate; etching the first transition layer up to the protection layer, to make a surface, away from the active structure layer, of the protection layer to be a planarization surface.

A FET channel includes a stack of silicon nanosheets. The silicon nanosheets are oriented parallel to a planar portion of the FET in which the FET channel is formed. The FET channel also includes a vertical blocker fin. The vertical blocker fin is attached to at least one nanosheet in the stack of nanosheets.

A method of manufacturing a semiconductor device includes forming a gate oxide layer on a substrate, where the substrate includes a high voltage region and a low voltage region. The gate oxide layer is disposed in the high voltage region. Wet etching is performed on the gate oxide layer to reduce a thickness of the gate oxide layer. Multiple trenches are formed around the high voltage region in the substrate, where forming the trenches includes removing an edge of the gate oxide layer to make the thickness of the gate oxide layer uniform. An insulating material is filled in the trenches to form multiple shallow trench isolation structures, where an upper surface of the shallow trench isolation structures close to the edge of the gate oxide layer is coplanar with an upper surface of the gate oxide layer.

A method of fabricating a semiconductor device is provided. The method includes: loading a substrate into a substrate processing apparatus; and processing the substrate, using the substrate processing apparatus. The processing the substrate includes: providing a process gas; generating a process etchant from the process gas, using plasma ignition, the process etchant including a first etchant and a second etchant; processing the substrate, using the process etchant; identifying a composition rate of the process etchant; and controlling the processing of the substrate based on a process result according to the composition rate of the process etchant.

Selective gas etching for self-aligned pattern transfer uses a first block and a separate second block formed in a sacrificial layer to transfer critical dimensions to a desired final layer using a selective gas etching process. The first block is a first hardmask material that can be plasma etched using a first gas, and the second block is a second hardmask material that can be plasma etched using a second gas separate from the first gas. The first hardmask material is not plasma etched using the second gas, and the second hardmask material is not plasma etched using the first gas.

The present disclosure provides a method for improving residue formation after mandrel removal, including steps of: providing a TEOS layer, forming mandrel structures spaced apart from each other on the TEOS layer, and forming spacers on sidewalls of each of the mandrel structures; forming a first SOC layer to cover the surface of the TEOS layer, the mandrel structures, and the spacers of the mandrel structures, and forming a SOC structure that covers the spacers and exposes the top surfaces of the mandrel structures; removing the mandrel structures by etch along sidewalls of SOC structure, forming a first groove between two of the spacers on the sidewalls of the removed mandrel structures; forming a second SOC layer to cover the SOC structure and fill the first groove; performing top planarization of the second SOC layer until the top surface of the SOC structure is exposed.

An electronic device and a manufacturing method are provided. The electronic device includes a first semiconductor chip, a second semiconductor chip and a third semiconductor chip. The second semiconductor chip is stacked on the first semiconductor chip, and is electrically connected to the first semiconductor chip by hybrid bonding. The third semiconductor chip is stacked on the second semiconductor chip, and is electrically connected to the second semiconductor chip through a plurality of bumps.