Methods and systems for depositing vanadium and/or indium layers onto a surface of a substrate and structures and devices formed using the methods are disclosed. An exemplary method includes using a cyclical deposition process, depositing a vanadium and/or indium layer onto the surface of the substrate. The cyclical deposition process can include providing a vanadium and/or indium precursor to the reaction chamber and separately providing a reactant to the reaction chamber. The cyclical deposition process may desirably be a thermal cyclical deposition process. Exemplary structures can include field effect transistor structures, such as gate all around structures. The vanadium and/or indium layers can be used, for example, as barrier layers or liners, as work function layers, as dipole shifter layers, or the like.

A memory device comprising a memory cell over a first transistor including silicon in a semiconductor layer is provided. The memory cell includes a capacitor and a second transistor over the capacitor. The capacitor includes a first conductor, a first insulator, and a second conductor that are stacked in this order. The second conductor serves as one of a source and a drain of the second transistor. A third conductor functioning as the other of the source and the drain of the second transistor is located over the second insulator. An opening reaching the second conductor is provided in the second insulator and the third conductor. An oxide semiconductor, a third insulator, and a fourth conductor are stacked in this order to overlap with the opening. The fourth conductor is electrically connected to a source or a drain of the first transistor.

In the method for cleaning a silicon wafer of this disclosure, an oxidizing agent is supplied in the surface layer modification process from a position shifted from the center of the silicon wafer in the radial direction. The method for producing a silicon wafer of this disclosure includes performing the above-mentioned method for cleaning a silicon wafer. When the silicon wafer of this disclosure is subjected to a given measurement, difference between maximum and minimum values of the thickness of the natural oxide film in the radial direction of the silicon wafer, when a thickness of the natural oxide film is normalized to a maximum value, is 0.1 or less.

A method includes forming a dummy gate stack on a first protruding structure of a wafer, wherein the first protruding structure comprises a first semiconductor layer, etching the dummy gate stack to form a trench in the dummy gate stack and to reveal the first semiconductor layer, and removing the first semiconductor layer and a semiconductor strip underlying the first semiconductor layer to extend the trench downwardly. The trench is filled with a dielectric material to form a dielectric isolation region. A backside grinding process is performed on a semiconductor substrate of the wafer. The dielectric isolation region is revealed from a backside of the wafer. A backside dielectric layer is formed. on the backside of the wafer, and the backside dielectric layer contacts the dielectric isolation region.

There is provided a technique that includes: forming a nitride film on a substrate by performing a cycle a predetermined number of times, the cycle including: (a) supplying a precursor to the substrate; (b) supplying a nitriding agent to the substrate; and (c) supplying an active species X, which is generated by plasma-exciting an inert gas, to the substrate, wherein a stress of the nitride film is controlled to be between a tensile stress and a compressive stress or is controlled to be the compressive stress by controlling an amount of exposure of the active species X to a surface of the substrate in (c).

A plasma processing apparatus generating plasma by electromagnetic waves supplied into a processing container to process a substrate, includes an upper electrode disposed in an upper portion of the processing container, a power supply member connected to the upper electrode to supply electromagnetic waves to the upper electrode, a first shield member and a second shield member configured to electrically shield the upper electrode and the power supply member, a ring-shaped insulating member provided between the upper electrode and the first shield member and between the upper electrode and the second shield member, and having a plurality of gas through-holes penetrating inside thereof, and a conductive member covering a first end of the insulating member and electrically interconnecting the first shield member and the second shield member. The power supply member passes through an inner space in the insulating member and supplies electromagnetic waves to the upper electrode.

A method of forming a partially silicided element is provided. A silicided structure including a silicide layer on a base structure is formed. A dielectric region is formed over the silicided structure. The dielectric region is etched to form a contact opening exposing a first area of the silicide layer and a tub opening exposing a second area of the silicide layer. A conformal metal is deposited to (a) fill the contact opening to define a contact and (b) form a cup-shaped metal structure in the tub opening. Another etch is performed to remove the cup-shaped metal structure in the tub opening, to remove the underlying silicide layer second area and to expose an underlying area of the base structure, wherein the silicide layer first area remains intact. The base structure with the intact silicide layer first area and removed silicide layer second area defines the partially silicided element.

Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In a method embodiment, a dielectric layer is formed on a semiconductor substrate. The semiconductor substrate has a source/drain region. An opening is formed through the dielectric layer to the source/drain region. A silicide region is formed on the source/drain region and a barrier layer is formed in the opening along sidewalls of the dielectric layer by a same Plasma-Enhance Chemical Vapor Deposition (PECVD) process.

Methods and apparatuses for precise trimming of silicon-containing materials are provided. Methods involve oxidizing silicon-containing materials and thermally removing the oxidized silicon-containing materials at particular temperatures for a self-limiting etch process. Methods also involve a surface reaction limited process using a halogen source and modulated temperature and exposure duration to etch small amounts of silicon-containing materials. Apparatuses are capable of flowing multiple oxidizers at particular temperature ranges to precisely etch substrates.

A plasma processing apparatus for generating plasma from a processing gas using microwaves and performing plasma processing on a substrate is provided. The apparatus includes a processing chamber having a substrate support on which the substrate is placed; a plurality of microwave radiation units arranged at a central portion and an outer peripheral portion of a ceiling wall of the processing chamber and configured to radiate microwaves; and a controller configured to complete microwave radiation from the microwave radiation unit in the central portion upon completion of plasma processing of the substrate and then complete microwave radiation from the microwave radiation units in the outer peripheral portion.