A semiconductor structure includes a high-k metal gate structure (HKMG) disposed over a channel region of a semiconductor layer formed over a substrate, where the HKMG includes an interfacial layer disposed over the semiconductor layer, a high-k dielectric layer disposed over the interfacial layer, and a gate electrode disposed over the high-k dielectric layer, where a length of the high-k dielectric layer is greater than a length of the gate electrode and where outer edges of the interfacial layer, the high-k dielectric layer, and the gate electrode form a step profile. The semiconductor structure further includes gate spacers having sidewall portions contacting sidewalls of the gate electrode and bottom portions contacting top portions of the high-k dielectric layer and the interfacial layer, and source/drain features disposed in the semiconductor layer adjacent to the HKMG.

Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary method comprises forming a fin over a substrate, wherein the fin comprises a first semiconductor layer and a second semiconductor layer including different semiconductor materials, and the fin comprises a channel region and a source/drain region; forming a dummy gate structure over the channel region of the fin and over the substrate; etching a portion of the fin in the source/drain region to form a trench therein, wherein a bottom surface of the trench is below a bottom surface of the second semiconductor layer; selectively removing an edge portion of the second semiconductor layer in the channel region such that the second semiconductor layer is recessed; forming a sacrificial structure around the recessed second semiconductor layer and over the bottom surface of the trench; and epitaxially growing a source/drain feature in the source/drain region of the fin.

A method includes removing a first dummy gate structure to form a recess around a first nanostructure and a second nanostructure; depositing a sacrificial layer in the recess with a flowable chemical vapor deposition (CVD); and patterning the sacrificial layer to leave a portion of the sacrificial layer between the first nanostructure and the second nanostructure. The method further include depositing a first work function metal in first recess; removing the first work function metal and the portion of the sacrificial layer from the recess; depositing a second work function metal in the recess, wherein the second work function metal is of an opposite type than the first work function metal; and depositing a fill metal over the second work function metal in the recess.

A semiconductor device includes a semiconductor substrate, a control gate, a select gate, a floating gate, a dielectric layer, a dielectric structure, and a spacer. The semiconductor substrate has a drain region, a source region, and a channel region between the drain region and the source region. The control gate is over the channel region of the semiconductor substrate. The select gate is over the channel region of the semiconductor substrate and separated from the control gate. The floating gate is between the control gate and the semiconductor substrate. The dielectric layer lines a sidewall of the floating gate. The dielectric structure is disposed below the select gate and adjacent to the dielectric layer. The dielectric structure interfaces a lower portion of a sidewall of the select gate. The select gate is between the spacer and the control gate. The spacer interfaces an upper portion of the select gate.

A semiconductor device includes a substrate including active regions, channel layers disposed in each of trenches extending from an upper surface of the active regions in a direction perpendicular to an upper surface of the substrate, and gate electrodes on the channel layers. Each of the channel layers includes a first single unit layer comprising a first oxide semiconductor, and the first single unit layer includes a first oxide in a first region, and a second oxide different from the first oxide in a second region, which is remaining portion of the first single unit layer.

A method includes depositing a dielectric layer over a substrate, and etching the dielectric layer to form an opening and to expose a first conductive feature underlying the dielectric layer. The dielectric layer is formed using a precursor including nitrogen therein. The method further includes depositing a sacrificial spacer layer extending into the opening, and patterning the sacrificial spacer layer to remove a bottom portion of the sacrificial spacer layer. A vertical portion of the sacrificial spacer layer in the opening and on sidewalls of the dielectric layer is left to form a ring. A second conductive feature is formed in the opening. The second conductive feature is encircled by the ring, and is over and electrically coupled to the first conductive feature. At least a portion of the ring is removed to form an air spacer.

A method of capping a metal layer includes performing a conversion process to reduce a metal oxide layer formed on a top surface of the metal layer and form a metal sulfide layer on the top surface of the metal layer, exposing the top surface of the metal layer to an oxidizing environment, and performing a removal process to remove the metal sulfide layer.

This disclosure relates to a semiconductor structure (100), comprising a crystalline silicon substrate (110), having a surface (111), and a crystalline silicon oxide superstructure (120) on the surface (111) of the silicon substrate (110), the silicon oxide superstructure (120) having a thickness of at least two molecular layers and a (11) plane structure using Wood's notation.

Methods for depositing hardmask materials and films, and more specifically, for depositing phosphorus-doped, silicon nitride films are provided. A method of depositing a material on a substrate in a processing chamber includes exposing a substrate to a deposition gas in the presence of RF power to deposit a phosphorus-doped, silicon nitride film on the substrate during a plasma-enhanced chemical vapor deposition (PE-CVD) process. The deposition gas contains one or more silicon precursors, one or more nitrogen precursors, one or more phosphorus precursors, and one or more carrier gases. The phosphorus-doped, silicon nitride film has a phosphorus concentration in a range from about 0.1 atomic percent (at %) to about 10 at %.

A method of manufacturing a composite structure comprises: a) providing a donor substrate of a single-crystal semiconductor material, b) implanting ions into the donor substrate, excluding an annular peripheral region, to form a buried brittle plane, the implantation conditions defining a first thermal budget for obtaining bubbling on a face of the donor substrate and a second thermal budget for obtaining a fracture in the brittle plane, c) forming a stiffening film on the donor substrate, carried out by applying a thermal budget lower than the first thermal budget, the stiffening film being perforated in the form of a mesh, the perforated stiffening film leaving a plurality of zones of the front face bare, d) depositing a carrier substrate on the donor substrate carried out by applying a thermal budget greater than the first thermal budget, and e) separating the donor substrate along the brittle plane.