A substrate processing method using a substrate processing apparatus which comprises a process chamber in which a reaction space is formed to process a substrate in which a composite layer pattern having a plurality of first insulating layers and a plurality of second insulating layers alternately stacked thereon is formed, a substrate support unit, a gas distribution unit, and a plasma reactor, the method comprising the steps of: heating the substrate support unit and the gas distribution unit such that a temperature of the gas distribution unit is maintained equal to or lower than a temperature of the substrate support unit; supplying a reactive gas including a halogen-containing gas to the plasma reactor; generating radicals by applying power to the plasma reactor to activate the halogen-containing gas; and at least partially etching the plurality of first insulating layers in a lateral direction selectively with respect to the plurality of second insulating layers by supplying the radicals onto the substrate mounted on the substrate support unit through the gas distribution unit.

Embodiments of the present invention provide a method for removing a barrier layer of a metal interconnection on a wafer, which remove a single-layer metal ruthenium barrier layer. A method comprises: oxidizing step, is to oxidize the single-layer metal ruthenium barrier layer into a ruthenium oxide layer by electrochemical anodic oxidation process; oxide layer etching step, is to etch the ruthenium oxide layer with etching liquid to remove the ruthenium oxide layer. The present invention also provides a method for removing a barrier layer of a metal interconnection on a wafer, using in a structure of a process node of 10 nm and below, wherein the structure comprises a substrate, a dielectric layer, a barrier layer and a metal layer, the dielectric layer is deposited on the substrate and recessed areas are formed on the dielectric layer, the barrier layer is deposited on the dielectric layer, the metal layer is deposited on the barrier layer, wherein the metal layer is a copper layer, the barrier layer is a single-layer metal ruthenium layer, and the method comprises: thinning step, is to thin the metal layer; removing step, is to remove the metal layer; oxidizing step, is to oxidize the barrier layer, and the oxidizing step uses an electrochemical anodic oxidation process; oxide layer etching step, is to etch the oxidized barrier layer.

A method for manufacturing raised strip-shaped active areas is disclosed, including: step 1: performing etching on a semiconductor substrate to form patterning raised strip-shaped structures and shallow trenches; step 2: forming a second dielectric layer which fills the shallow trenches and extends to a surface of the first hard mask layer on top surfaces of the raised strip-shaped structures; step 3: performing the first CMP on second dielectric layer, the first CMP stops at a surface of a first hard mask layer; step 4: performing planarization adjustment on a top surface of the second dielectric layer through second wet etching to reduce a height difference of the top surface of the second dielectric layer in different areas; step 5: removing the first hard mask layer; and step 6: performing third dry etching to reduce the top surface of the second dielectric layer to below the top surface of each raised strip-shaped structure.

A method of manufacturing a semiconductor device includes depositing a dielectric layer over a substrate, performing a first patterning to form an opening in the dielectric layer, and depositing an oxide film over and contacting the dielectric layer and within the opening in the dielectric layer. The oxide film is formed from multiple precursors that are free of O.sub.2, and depositing the oxide film includes forming a plasma of a first precursor of the multiple precursors.

There is provided a technique that includes: (a) supplying a first gas containing a predetermined element to the substrate; (b) supplying a second gas containing carbon and nitrogen to the substrate; (c) supplying a nitrogen-containing gas activated by plasma to the substrate; (d) supplying an oxygen-containing gas to the substrate; and (e) forming a film containing at least the predetermined element, oxygen, carbon, and nitrogen on the substrate by: performing a cycle a first number of times of two or more, the cycle performing (a) to (d); or performing a cycle once or more, the cycle performing (a) to (d) in this order.

According to one embodiment, a semiconductor device includes a first electrode, a second electrode, a third electrode, a first nitride region, a second nitride region, and a third nitride region. The first nitride region includes Al.sub.x1Ga.sub.1-x1N (0x1<1). The first nitride region includes a first partial region, a second partial region, a third partial region, a fourth partial region, and a fifth partial region. The second nitride region includes Al.sub.x2Ga.sub.1-x2N (x1<x21) or In.sub.yAl.sub.zGa.sub.(1-y-z)N (0<y1, 0z<1, y+z1). The second nitride region includes a sixth partial region. The third nitride region includes Al.sub.x3Ga.sub.1-x3N (x1<x3<x2). The third nitride region includes a seventh partial region.

An antiferroelectric field effect transistor (Anti-FeFET) of a memory cell includes an antiferroelectric layer instead of a ferroelectric layer. The antiferroelectric layer may operate based on a programmed state and an erased state in which the antiferroelectric layer is in a fully polarized alignment and a non-polarized alignment (or a random state of polarization), respectively. This enables the antiferroelectric layer in the FeFET to provide a sharper/larger voltage drop for an erase operation of the FeFET (e.g., in which the FeFET switches or transitions from the programmed state to the erased state) relative to a ferroelectric material layer that operates based on switching between two opposing fully polarized states.

A method of processing a substrate that includes: forming a bottom passivation layer including an oxide over a first portion of a dielectric layer at a bottom of a recess of the substrate, the recess having sidewalls including a second portion of the dielectric layer; and performing a lateral etch to etch the second portion of the dielectric layer, the bottom passivation layer covering the first portion of the dielectric layer during the lateral etch, and where the forming of the bottom passivation layer includes exposing the substrate to a first plasma including a halogen, and exposing the substrate to a second plasma including oxygen to form the bottom passivation layer.

Exemplary integrated cluster tools may include a factory interface including a first transfer robot. The tools may include a wet clean system coupled with the factory interface at a first side of the wet clean system. The tools may include a load lock chamber coupled with the wet clean system at a second side of the wet clean system opposite the first side of the wet clean system. The tools may include a first transfer chamber coupled with the load lock chamber. The first transfer chamber may include a second transfer robot. The tools may include a thermal treatment chamber coupled with the first transfer chamber. The tools may include a second transfer chamber coupled with the first transfer chamber. The second transfer chamber may include a third transfer robot. The tools may include a metal deposition chamber coupled with the second transfer chamber.

A method is presented for selective deposition on metals using porous low-k materials. The method includes forming alternating layers of a porous dielectric material and a first conductive material, forming a surface aligned monolayer (SAM) over the first conductive material, depositing hydroxamic acid (HA) material over the porous dielectric material, growing an oxide material over the first conductive material, removing the SAM, depositing a dielectric layer adjacent the oxide material, and replacing the oxide material with a second conductive material defining a bottom electrode.