A method for forming a semiconductor device includes followings. A metal layer is formed to embedded in a first dielectric layer. An etch stop layer is formed over the metal layer and the first dielectric layer. A second dielectric layer is formed over the etch stop layer. A portion of the second dielectric layer is removed to expose a portion of the etch stop layer and to form a via by a dry etching process. The portion of the etch stop layer exposed by the second dielectric layer is removed to expose the metal layer and to form a damascene cavity by a wet etching process. A damascene structure is formed in the damascene cavity.

The present application provides a method for fabricating multiple work function layers, including: forming the first to the nth transistor gates with notches; forming a blocking layer in the notches; depositing the first work function layer and removing the first work function layer on the first to the (n1)th transistor gates; depositing a second work function layer; removing the second work function layer on the first to the (n2)th transistor gates; depositing a third work function layer on the blocking layer on the first to the (n2)th transistor gates and the second work function layer on the (n1)th and nth transistor gates; removing the third work function layer on the first to (n3)th transistor gates; depositing the third to the (n1)th work function layers by analogy until only the blocking layer exists on the last transistor gate, herein the thickness of the third to the (n1)th work function layers decreases sequentially and gradually.

Dielectric films for semiconductor devices and methods of forming. A processing method includes forming a first film of a first dielectric material on a substrate by performing a first plurality of cycles of atomic layer deposition and, thereafter, heat-treating the first film, where a thickness of the first film is below a threshold thickness needed for spontaneous polarization in the first dielectric material. The processing method further includes forming a second film of a second dielectric material on the substrate by performing a second plurality of cycles of atomic layer deposition and, thereafter, heat-treating the second film, where a thickness of the second film is greater than the thickness of the first film, and the second film is ferroelectric or antiferroelectric. The first and second dielectric materials can include at least one metal oxide, for example zirconium oxide, hafnium oxide, or a laminate or mixture thereof.

A method for vacuum gap formation on a dielectric substrate uses area selective deposition (ASD), such as atomic layer deposition (ALD) or chemical vapor deposition (CVD), of a hardmask material on a substrate patterned with a self-assembled monolayer (SAM) and metal features. Due to the presence of the SAM, the hardmask material reaches, but does not touch the metal features leaving areas that will form gaps on the resultant hardmask when the SAM is removed from the substrate. Etching of the dielectric substrate forms trenches in the areas of the gaps. When a non-conformal coating is deposited on the dielectric substrate, vacuum gaps form in the trenches as the non-conformal coating enters into the trenches, but closes off at the surface of the substrate prior to the complete filling of the trench.

A substrate processing method includes preparing a substrate having a target film including silicon, carbon, and nitrogen on a surface of the substrate; supplying hydrogen gas and oxygen gas to the target film to oxidize a surface layer of the target film and form an oxide film; and etching the oxide film.

The present disclosure provides a method for forming an integrated circuit (IC) structure. The method comprises providing a substrate including a conductive feature; forming aluminum (Al)-containing dielectric layer on the conductive feature; forming a low-k dielectric layer on the Al-containing dielectric layer; and etching the low-k dielectric layer to form a contact trench aligned with the conductive feature. A bottom of the contact trench is on a surface of the Al-containing dielectric layer.

Examples are disclosed relate to using an inhibitor with a silicon oxide ALD deposition process to refill recesses in STI regions. One example provides a method of processing a substrate. The method comprises depositing an inhibitor on the substrate, wherein a concentration of the inhibitor on a gate structure of the substrate is greater relative to the concentration of the inhibitor on a recessed shallow trench isolation (STI) region of the substrate. The method further comprises depositing a layer of silicon oxide on the substrate, the inhibitor inhibiting growth of the layer of silicon oxide such that the layer of silicon oxide is thicker on the recessed STI region and thinner on the gate structure.

Embodiments of improved process flows and methods are provided to pattern a semiconductor substrate using direct self-assembly (DSA) of metalate salt ionic liquid crystals (ILCs) having metalate anions. After self-assembly of the metalate salt ILCs into ordered structures, an oxidation process is used to remove the organic components of the ordered structures and convert the metalate anions into metal oxide patterns. In addition to providing a robust metal oxide pattern, which can be transferred to the underlying substrate, the process flows and methods disclosed herein enable ILCs to be used as pitch multipliers in advanced patterning techniques.

The present application discloses a support bracing structure, a semiconductor device with the support bracing structure, and a method for fabricating the semiconductor device with the support bracing structure. The support bracing structure includes a first bracing layer including two connection portions respectively positioned on top surfaces of two adjacent bottom electrodes, and a frame portion bridging the two connection portions; and a protection layer including a first portion positioned on and conforming to an inner surface of the frame portion and positioned between the two connection portions. The inner surface of the frame portion is normal to the top surfaces of the two adjacent bottom electrodes.

A semiconductor device includes a fin structure that protrudes vertically out of a substrate, wherein the fin structure contains silicon germanium (SiGe). An epi-silicon layer is disposed on a sidewall of the fin structure. The epi-silicon layer contains nitrogen. One or more dielectric liner layers are disposed on the epi-silicon layer. A dielectric isolation structure is disposed over the one or more dielectric liner layers.