A semiconductor device according to the present disclosure includes a bottom dielectric feature on a substrate, a plurality of channel members directly over the bottom dielectric feature, a gate structure wrapping around each of the plurality of channel members, two first epitaxial features sandwiching the bottom dielectric feature along a first direction, and two second epitaxial features sandwiching the plurality of channel members along the first direction.

A microelectronic device comprises a stack structure, a contact structure, a liner material, and a boron-containing material. The stack structure comprises alternating conductive structures and dielectric structures. The contact structure extends through the stack structure. The liner material is between the stack structure and the contact structure. The boron-containing material is between the liner material and the stack structure. Related electronic systems and methods are also described.

A super junction device with an increased voltage rating may be formed by decreasing the width of the P-type region and increasing the doping concentration, while also increasing the height of the overall device. A trench may be etched for both a P-type region and an adjacent N-type region. This allows the height of the overall device to be increased while maintaining a feasible aspect ratio to fill the trench. The P-type material may then be formed by doping the sidewalls of the trench for a P-type layer that is relatively thin compared to the remaining width of the trench. The trench may then be filled with N-type material such that the P-type region fills the space between the N-type regions without any voids or seams, while having a width that would be unattainable using traditional etch-and-fill methods for the P-type region alone.

According to one aspect of the technique, there is provided a method of manufacturing a semiconductor device, including: modifying a surface of a substrate into an impurity-containing layer by performing: (a) supplying an impurity-containing gas containing an impurity and a dilution gas into a process chamber in which the substrate is accommodated; (b) plasma-exciting the impurity-containing gas and the dilution gas; and (c) supplying an active species containing the impurity generated by plasma-exciting the impurity-containing gas and the dilution gas to the substrate, wherein a flow rate ratio of the impurity-containing gas to the dilution gas is controlled in (a) such that a partial pressure of the impurity-containing gas in the process chamber is set to a predetermined partial pressure less than a partial pressure at which the impurity-containing gas forms deposits containing a polymer in the process chamber.

A method for manufacturing a semiconductor device includes preparing a structure body including a semiconductor part, a trench being formed in the structure body. The trench extends along a first direction. The method includes forming a doped glass film at an upper surface of the structure body and at a surface of the trench, forming a resist pattern on the structure body and performing lithography, removing the doped glass film at a location other than a location at which the resist pattern remains, and performing annealing treatment of the structure body including the doped glass film that remains.