A second gate electrode is adjacent, in a Y direction, to a first tip of a semiconductor layer in a first active region such that a protruding distance of a second tip of the second gate electrode protruded, in a X direction, from the semiconductor layer in the first active region is greater than or equal to 0. Also, the first tip of the semiconductor layer in the first active region is covered with a second sidewall spacer. Further, a first epitaxial layer and the second gate electrode are electrically connected to each other via a first shared contact plug formed so as to across the first epitaxial layer, the second sidewall spacer and the second gate electrode.

Provided are a substrate for epitaxially growing a diamond crystal, having at least a surface made of a metal, in which the above surface made of the metal is a plane having an off angle of more than 0, and the full width at half maximum of the X-ray diffraction peak from the (002) plane by the X-ray rocking curve measurement at the above surface made of the metal is 300 seconds or less; and a method of manufacturing a diamond crystal, including epitaxially growing a diamond crystal on the above surface made of the metal of the above substrate.

A method for preparing a super junction trench MOSFET, comprising: providing a substrate, and forming a first trench in the substrate; depositing an epitaxial portion of a first stage in the first trench while supplying a doped gas and an etching gas, and performing an epitaxial process after stopping supplying the doped gas and the etching gas, wherein impurities in the epitaxial portion of the first stage are diffused to an upper portion of the first trench and to form an epitaxial portion of a second stage with a gradient concentration by utilizing a high-temperature environment of the epitaxial process; forming a well region, a trench gate, and an active region in the substrate at a periphery of the first trench; forming an interlayer dielectric layer covering the column, the trench gate, and the active region; and electrically leading out the column, the trench gate, and the active region.

A method includes providing a substrate having a first semiconductor material; creating a mask that covers an nFET region of the substrate; etching a pFET region of the substrate to form a trench; epitaxially growing a second semiconductor material in the trench, wherein the second semiconductor material is different from the first semiconductor material; and patterning the nFET region and the pFET region to produce a first fin in the nFET region and a second fin in the pFET region, wherein the first fin includes the first semiconductor material and the second fin includes a top portion over a bottom portion, wherein the top portion includes the second semiconductor material, and the bottom portion includes the first semiconductor material.

A capacitor is provided for high temperature systems. The capacitor includes: a substrate formed from silicon carbide material; a dielectric stack layer, including a first layer deposited on the substrate and a second layer deposited on the first layer; a Schottky contact layer deposited on the second layer; and an Ohmic contact layer deposited on the substrate. The first layer is formed with aluminum nitride (AlN) epitaxially, and the second layer is formed with aluminum oxide (Al.sub.2O.sub.3). AlN and Al.sub.2O.sub.3 are ultrawide band gap materials, and as a result, they can be use as the dielectric in the capacitor, allowing the capacitance changes to be less than 10% between 250 C. and 600 C., which is very effective for the high temperature systems.

A method of Selective Area Epitaxy (SAE) on a semiconductor wafer is disclosed. A dielectric mask is deposited on the wafer surface to define an opening for epitaxial growth. The mask includes a zigzag edge formed by successive straight facets oriented to avoid crystallographic directions associated with unintentional growth enhancement. During SAE, a semiconductor layer is grown in the opening such that edge-growth enhancement at the zigzag edge is suppressed relative to straight edges aligned with [011] or [0 11] directions. By replacing straight mask edges with zigzag geometry, fragile linear overgrowth is avoided, reducing particulate contamination and improving device reliability. The zigzag edge may be tailored by pitch, amplitude, or facet orientation, including angles such as 34, 56, 124, or 146 relative to [011]. The method is applicable to III-V materials, including InP-based photonic integrated circuits, lasers, modulators, and amplifiers.

A processing chamber with a top, a bottom, and a sidewall coupled together to define an enclosure, a substrate support having a substrate supporting surface, an energy source coupled to the top or the bottom, and a gas injector liner disposed at the sidewall. The gas injector liner comprises a first plurality of gas outlets disposed at a first height, wherein one or more of the first plurality of gas outlets are oriented upwardly or downwardly, a second plurality of gas outlets disposed at a second height shorter than the first height, wherein one or more of the second plurality of gas outlets are oriented upwardly or downwardly, and a third plurality of gas outlets disposed at a third height shorter than the second height, wherein one or more of the third plurality of gas outlets are oriented upwardly or downwardly with respect to the substrate supporting surface.