Semiconductor Device With Selective Area Epitaxy Growth Utilizing a Mask to Suppress or Enhance Growth at the Edges

Abstract

A method of Selective Area Epitaxy (SAE) on a semiconductor wafer is disclosed. A dielectric mask is deposited on the wafer surface to define an opening for epitaxial growth. The mask includes a zigzag edge formed by successive straight facets oriented to avoid crystallographic directions associated with unintentional growth enhancement. During SAE, a semiconductor layer is grown in the opening such that edge-growth enhancement at the zigzag edge is suppressed relative to straight edges aligned with [011] or [0 11] directions. By replacing straight mask edges with zigzag geometry, fragile linear overgrowth is avoided, reducing particulate contamination and improving device reliability. The zigzag edge may be tailored by pitch, amplitude, or facet orientation, including angles such as 34, 56, 124, or 146 relative to [011]. The method is applicable to III-V materials, including InP-based photonic integrated circuits, lasers, modulators, and amplifiers.

Claims

1. A method of Selective Area Epitaxy (SAE) on a semiconductor wafer, comprising: depositing a dielectric mask on a surface of the semiconductor wafer, the dielectric mask covering a first area of the surface and leaving a second area of the surface exposed as an opening for epitaxial growth, the dielectric mask including a zigzag edge at a boundary between the first area and the second area; and growing, by SAE, a semiconductor layer in the second area such that edge-growth enhancement at the zigzag edge is suppressed relative to a straight mask edge aligned parallel to a crystallographic direction of enhanced growth of the semiconductor wafer.

2. The method of claim 1, wherein the semiconductor wafer comprises indium phosphide (InP) oriented in or near a (100) crystal plane.

3. The method of claim 1, wherein the crystallographic direction of enhanced growth comprises a [011] or [0-1-1] direction of the semiconductor wafer.

4. The method of claim 1, wherein the dielectric mask comprises silicon dioxide (SiO.sub.2), silicon nitride (Si.sub.3N.sub.4), or a combination thereof.

5. The method of claim 1, wherein straight facets of the zigzag edge are oriented at one or more angles of approximately 34, 124, 214, or 304 relative to a [011] direction.

6. The method of claim 5, wherein straight facets of the zigzag edge are oriented at one or more angles of approximately 56, 146, 236, or 326 relative to the [011] direction.

7. The method of claim 1, wherein the zigzag edge comprises two alternating facet orientations that differ by 20 to 120 in a plane of the wafer.

8. The method of claim 1, wherein no individual straight facet of the zigzag edge exceeds 10 m in length without a change in orientation.

9. The method of claim 1, wherein the zigzag edge is disposed along portions of the dielectric mask oriented within 15 of [011] or [0-1-1] directions of the semiconductor wafer.

10. The method of claim 1, wherein the SAE is performed in a metal-organic chemical vapor deposition (MOCVD) reactor under conditions that promote epitaxy on the second area and inhibit deposition on the dielectric mask.

11. The method of claim 1, wherein the semiconductor layer comprises indium phosphide (InP), indium gallium arsenide (InGaAs), indium gallium arsenide phosphide (InGaAsP), or aluminum indium gallium arsenide (AlInGaAs).

12. The method of claim 1, further comprising, subsequent to the growing, integrating the semiconductor layer into a photonic integrated circuit comprising at least one of: a modulator, a semiconductor optical amplifier, a laser, a detector, a variable optical attenuator, or a phase shifter.

13. A semiconductor device formed by Selective Area Epitaxy (SAE), comprising: a semiconductor wafer having a surface; a dielectric mask disposed on the surface and covering a first area of the surface, the dielectric mask leaving a second area of the surface exposed as an opening for epitaxial growth; the dielectric mask including a zigzag edge at a boundary between the first area and the second area; and a semiconductor epitaxial layer grown in the second area such that edge-growth enhancement at the zigzag edge is suppressed relative to a straight mask edge aligned parallel to a crystallographic direction of enhanced growth of the semiconductor wafer.

14. The semiconductor device of claim 13, wherein the semiconductor wafer comprises indium phosphide (InP) oriented in or near a (100) crystal plane.

15. The semiconductor device of claim 13, wherein the crystallographic direction of enhanced growth comprises a [011] or [0-1-1] direction of the semiconductor wafer.

16. The semiconductor device of claim 13, wherein the dielectric mask comprises silicon dioxide (SiO.sub.2), silicon nitride (Si.sub.3N.sub.4), or a combination thereof.

17. The semiconductor device of claim 13, wherein straight facets of the zigzag edge are oriented at one or more angles of approximately 34, 124, 214, or 304 relative to a [011] direction.

18. The semiconductor device of claim 17, wherein straight facets of the zigzag edge are oriented at one or more angles of approximately 56, 146, 236, or 326 relative to the [011] direction.

19. The semiconductor device of claim 13, wherein no individual straight facet of the zigzag edge exceeds 10 m in length without a change in orientation.

20. The semiconductor device of claim 13, wherein the semiconductor epitaxial layer forms part of a photonic integrated circuit comprising at least one of: a modulator, a semiconductor optical amplifier, a laser, a detector, a variable optical attenuator, or a phase shifter.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The present disclosure is illustrated and described herein with reference to the various drawings, in which like reference numbers are used to denote like system components/method steps, as appropriate, and in which:

[0021] FIGS. 1A and 1B are a series of schematic diagrams illustrating conventional strongly-guided and weakly-guided (shallow ridge) waveguides, respectively;

[0022] FIGS. 2A and 2B are a series of schematic diagrams illustrating the fabrication of conventional BH lasers or SOA structures;

[0023] FIG. 3 is a series of schematic diagrams illustrating the fabrication of a conventional gain element;

[0024] FIG. 4 is a series of schematic diagrams illustrating the fabrication of one exemplary embodiment of the gain element of the present disclosure;

[0025] FIG. 5 is a series of schematic diagrams illustrating the fabrication of another exemplary embodiment of the gain element of the present disclosure, as well as the coupling of the associated SOA and modulator;

[0026] FIG. 6 is a schematic diagram illustrating the flaring of a waveguide SOA or modulator width to match an associated modulator SOA optical mode in accordance with the methods of the present disclosure;

[0027] FIG. 7 is another schematic diagram illustrating the flaring of a waveguide modulator width to match an SOA optical mode in accordance with the methods of the present disclosure;

[0028] FIG. 8 is a schematic diagram illustrating a novel geometry for the edge of a mask used to overgrow an epitaxial layer in accordance with the methods of the present disclosure, suppressing undesirable growth enhancement.

[0029] FIGS. 9A-9D are block diagrams illustrating steps in an SAE growth process on a wafer to illustrate excess growth at edges of a mask;

[0030] FIG. 10 is a photograph of an actual wafer after the step in FIG. 9D;

[0031] FIG. 11A is a top view of a wafer illustrating a region;

[0032] FIG. 11B is a photograph of the wafer illustrating the region and excess growth that extends over the mask;

[0033] FIGS. 12A and 12B are photographs illustrating a cross-section of the P island from FIGS. 9A-9D in the direction of a waveguide (FIG. 12A) and perpendicular to the waveguide (FIG. 12B).

[0034] FIG. 13 is a diagram of a wafer, namely an InP wafer oriented in the (100) plane having a major flat and a minor flat perpendicular to the major flat, and a graph of preferred directions of the wafer;

[0035] FIG. 14 is a diagram of a rectangular mask with an angled orientation according to the series 2 and a zigzag-shaped mask with variable angles from both the series 1, 2;

[0036] FIG. 15 is a diagram of the InP wafer with an example mask placed thereon;

[0037] FIG. 16 is a diagram of the InP wafer with an example mask 12B placed thereon;

[0038] FIG. 17 is a flowchart of a process of growing an epitaxial layer onto a semiconductor wafer for a semiconductor device; and

[0039] FIG. 18 is a photograph of a circular mask within a high-resolution Field of View (FOV), to illustrate how the preferred angles were determined.

DETAILED DESCRIPTION OF THE DISCLOSURE

[0040] Again, the present disclosure provides a design whereby an optical amplifier is efficiently monolithically integrated with a deeply-etched ridge waveguide modulator, and, in particular, a multi-growth modulator formed on an InP wafer, such as that provided in U.S. Pat. No. 9,182,546, for example. The design enables the re-use of existing undoped overgrowth in the TWE modulator for the purpose of current blocking. Subsequent deep etching of the current-blocked buried ridge provides for independent control of the confinement factor and enables efficient coupling to a deeply-etched modulator. Thus, the present disclosure provides a means to re-use an overgrowth that already exists in the standard modulator process sequence, thereby reducing cost, complexity, and problems associated with many epitaxial growths, such as reliability issues. The present disclosure provides better current confinement, and therefore better electrical efficiency, than alternative shallow ridge solutions. The present disclosure decouples current confinement (provided by i-InP blocks described in greater detail herein below) from optical confinement (provided by etched areas described in greater detail herein below). Accordingly, the present disclosure provides an efficient alternative means to couple light from the modulator to the gain section without introducing an additional or new optical element into the design, such as that provided in U.S. Pat. No. 7,184,207, for example.

[0041] In general, the present disclosure provides a modulator with an optical amplifier, including: an N-type layer; a multi-quantum well material disposed on the N-type layer; a P-type layer disposed on the multi-quantum well material opposite the N-type layer; wherein a portion of the N-type layer, the multi-quantum well material, and a portion of the P-type layer collectively form a ridge structure; and a material that is not intentionally doped (undoped, or i-type) disposed on the N-type layer and about side portions of the ridge structure using selective area epitaxy. Optionally, the i-type material is further deeply etched to form a strongly guided structure. The N-type layer includes NInP. The P-type layer includes one of PInGaAs and PInP. The i-type material includes i-InP, but may alternatively be any type of suitable current-blocking material that impedes current flow, such as semi-insulating iron-doped InP. Optionally, over all or some portion of the length, a width of the strongly guided structure is selected to couple efficiently to a strongly guided modulator waveguide.

Monolithically Integrated Gain Element

[0042] FIG. 3 illustrates the fabrication of a conventional modulator structure 25, such as by the process provided in U.S. Pat. No. 9,182,546, for example. The modulator structure 25 is fabricated by blanketing the N-type wafer 10 with a first growth of MQW material 12 and a P-type layer 18. In a i-type ridge embodiment, a selective etch of the P-type layer 18 is then performed, and a u-InP layer 20 is selectively grown in the etched area. The P-type layer 18 and MQW material 12 are then selectively etched, leaving a i-InP-capped ridge in the i-type ridge SOA embodiment and a P-type-capped ridge in a P-type ridge modulator embodiment. Thus, a selective i-type growth step is typically utilized. It is still desirable to monolithically integrate a SOA with a modulator and provide performance that approximates that of a BH structure 15 (FIGS. 2A and 2B), without the introduction of a critically-aligned growth step. It is also still desirable to, for the monolithically integrated SOA, create a BH-like structure that has a lateral optical mode that is compatible for optical coupling to a deeply etched modulator ridge.

[0043] Referring now specifically to FIG. 4, in an embodiment, the gain element structure 35 of the present disclosure is fabricated by blanketing an N-type layer 10 with a first growth of optical gain material 12 and a P-type layer 18. The P-type layer 18, optical gain material 12, and N-type layer 10 are then selectively etched, leaving a P-capped ridge that is covered with a mask 19. An i-type growth step is then utilized to fill the lateral areas of the ridge with i-InP material 20. Here, the lateral i-InP material 20 provides superior current blocking, without the extra growth steps and critical alignments associated with BH fabrication

[0044] FIG. 5 is a series of schematic diagrams illustrating the fabrication of another exemplary embodiment of the gain element structure 35 of the present disclosure, as well as the means for coupling of the associated SOA 37 and modulator 39. The i-InP material 20 and N-type material 10 are etched to form i-InP material walls on either side of the ridge, thereby providing strong guiding on either side of the ridge. Further, the deeply etched modulator waveguide can be widened to provide lateral optical matching. It will be appreciated that, in FIG. 5, the bottom schematic represents the modulator waveguide that has been width-matched to the SOA input/output waveguide, shown in the middle schematic. For the SOA 37, W1 (current confinement) and W2 (optical mode overlap) can be varied independently, allowing the gain to be varied along the length of the SOA 37, for example to mitigate the effects of spatial hole burning.

[0045] FIG. 6 is a schematic diagram illustrating the flaring of a waveguide SOA or modulator width to match an associated modulator SOA optical mode in accordance with the methods of the present disclosure. Any arbitrary combination of central width and exterior width, with tapers in between, is possible. For example, only the central portion could be tapered, omitting the leading and trailing constant sections. This provides practical advantages for spatial hole burning by having high optical confinement at the beginning, and increasing injection, but lowering optical overlap at the end.

[0046] FIG. 7 is another schematic diagram illustrating the flaring of the waveguide modulator width to match the SOA optical mode in accordance with the methods of the present disclosure. Here, the SOA waveguide 37 is coupled to the modulator waveguide 39 via a tapering passive waveguide 38 or a tapering portion of the SOA waveguide 37 or modulator waveguide 39.

[0047] In the conventional modulator structure 25 of FIG. 3, there is already a selective growth of i-InP layer 20, the thickness of which may be determined by the optimization of the modulator design. This same growth is used herein to provide better current blocking for a SOA. As shown in FIG. 4, the i-InP layer 20 from the conventional modulator may also be deposited on either side of the SOA ridge 19. The design requirements of the modulator 25, however, may not provide a thickness of i-InP layer 20 sufficient to match the height of the SOA ridge 19. To improve the manufacturability of subsequent processing steps, enhanced growth may be used to make a more planar top surface. It should be noted that, for regions not requiring the increased lateral confinement of the current-blocking mesa, width can be increased so as to improve the thermal impedance of the SOA. For increased lateral optical confinement (to match the modulator mode and/or improve SOA efficiency), the deep etch ridge can be used.

Semiconductor Device with Suppressed or Enhanced Selective Area Epitaxy (SAE) Growth

[0048] Also, the present disclosure relates to systems and methods for a semiconductor device with Selective Area Epitaxy (SAE) growth utilizing a mask to suppress or enhance growth at the edges. Again, SAE is a technique for crystal growth on semiconductor surfaces. Areas of the wafer are covered or masked by thin layers of dielectric material (e.g., SiO.sub.2, Si.sub.3N.sub.4, etc.). In a crystal growth reactor, such as a Metal-Organic Vapor-Phase Deposition (MOCVD) chamber, crystal growth proceeds selectively only on those areas not covered by the mask. This disclosure provides a process for producing a semiconductor device containing areas of selective growth in an arbitrary orientation without unwanted growth enhancement and corresponding defects at the exterior edges of the masked areas. Specifically, the process includes variable profiles on the mask edges that can be used to suppress or enhance growth at the edges.

[0049] By way of an enabling technology, FIG. 8 illustrates a novel geometry 50 for the edge of a mask used to overgrow an epitaxial layer. There is often an undesirable degree of enhanced crystal growth that occurs at the mask edge where the pattern is in the [011] or [0-11] directions, for example. The use of a non-linear geometry 50 for the mask edge suppresses this undesirable growth enhancement. The use of a zigzag pattern on the mask edge, rather than a straight edge, is a novel solution. Unintentional growth enhancement at a mask edge is an ongoing problem in selective area growth. Solutions to date have focused on altering the growth conditions for the epitaxial growth. Selective area epitaxy is a technique that is used in the production of many InP optical modulators. This technique and the use of mask patterns to reduce unintentional enhancement are related to multi-growth modulators on InP wafer as described in U.S. Pat. No. 9,182,546. Suppressing unintentional enhancement by changing growth conditions has the disadvantage of also suppressing the intentional growth enhancement, which is often the purpose of pursuing selective area growth in the first place. The conventional use of straight-sided selective area masks (SAMs) leads to linear structures of enhanced growth material along the mask edge that are fragile and break off to cause contamination of the device surface, which has an adverse effect on manufacturability and reliability. The use of a geometric solution 50 suppresses the intentional growth enhancement at the edge of the mask without compromising the intended growth enhancement. The effect of unintentional enhancement at a mask edge is anisotropic on the wafer surface. Along one directional axis, the effect is strong, but along the perpendicular axis it is weak. By placing a zigzag pattern 50 along the edge susceptible to enhancement, almost none of that boundary is parallel to the line along which the unintentional enhancement occurs.

[0050] FIGS. 9A-9D are block diagrams illustrating steps in an SAE growth process 95 on a wafer 100 to illustrate excess growth at edges of a mask 102. The wafer 100 can be a wafer including a wafer 104, a P island 106 of Indium Phosphide (InP), and a contact layer 108 including, e.g., Indium gallium arsenide (InGaAs). The mask 102 can include SiO.sub.2, and is deposited (applied) to the contact layer 108 at FIG. 9A. In FIG. 9B, a region is etched away through the mask 102, the P island 106, and the contact layer 108. In FIG. 9C, SAE growth is performed in the etched region. Note, there is no SAE growth over the mask 100. In FIG. 9D, the mask 100 is removed. FIGS. 9C and 9D include excess growth 110 at the edge of the mask 100.

[0051] FIG. 10 is a photograph of FIG. 9D in an actual wafer 100. Specifically, this illustrates the traditional use of straight-sided SAE masks 102 that leads to linear structures of enhanced growth 110 material along the mask edge that are fragile and break off to form contamination of the device surface, which has an adverse effect on manufacturability and reliability. FIG. 10 illustrates how, in the clean-up of the residual oxide, the excess growth 110 fractures along the edge of the P island 106 parallel to the major flat, but the edge parallel to the minor flat (perpendicular to the length of the waveguides) is clean.

[0052] FIG. 11A is a top view of a wafer 100 illustrating a region 140, and FIG. 11B is a photograph of the wafer 100 illustrating the region 140 and excess growth 110 that extends over the mask 102. The bare wafer is masked with oxide and has a thick overgrowth of InP in the region 140. This creates a cap of extra growth that overhangs the oxide. A subsequent etch is enough to remove the oxide under the cap, but it also tends to break off other material.

[0053] FIGS. 12A and 12B are photographs illustrating a cross-section of the P island 106 in the direction of a waveguide (FIG. 12A) and perpendicular to the waveguide (FIG. 12B). It is noted in FIG. 12A the interface is well behaved in the direction of the waveguide. FIG. 12B, on the other hand, shows the excess growth broken off after the wet clean up. Prior to this, there is a large mushroom cap shape of InP. This feature leaves residual columns of material when subsequently etched.

[0054] Variously, the present disclosure notes that specific, preferred angles for the mask 102, the adaptation of a shape and/or orientation of the mask 102, and/or zigzag edges of the mask 102 can lead to suppression (or enhancement) of growth at the edges of the mask 102. That is, the mask 102 includes a specific geometry that suppresses or enhances the intentional growth enhancement at the edge of the mask 102 without compromising the intended growth enhancement, which is the purpose of SAE. The effect of unintentional enhancement at a mask edge is anisotropic on the wafer surface, i.e., it has a different value when measured in a different direction. Along one directional axis, the effect is strong, but along the perpendicular axis, it is weak. This is illustrated in FIGS. 12A and 12B.

[0055] In an embodiment, by placing a zigzag pattern or other angular patterns along the edge susceptible to enhancement, almost none of that boundary is parallel to the line along which the unintentional enhancement occurs.

[0056] Through growth experiments on III-V semiconductor materials (specifically, InP wafers oriented in the (100) plane), it has been determined that mask 102 edges aligned along certain crystallographic axes exhibit an undesirable degree of enhanced crystal growth, particularly in the [011] or [011] directions. Unfortunately for many semiconductor devices such as Photonic Integrated Circuits (PIC), these directions are the preferred primary axes of orientation. SAE masks 102, which are typically rectangular in shape, tend to be oriented along such directions to align with the device footprint and avoid wasting space. That is, conventional processes tend to orient conventional masks 102, which are rectangular with the wafer 100. The present disclosure proposes off-angled orientation as well as different geometric shapes for the masks 102, to avoid excess growth in the preferred primary axes of orientation.

[0057] Also, it has been determined that the converse of the above is also true: along specific crystallographic directions the undesirable enhanced crystal growth is suppressed and, indeed, transits through zero enhancement as a function of angle relative to the [011] or [011] axes. FIG. 13 is a diagram of an InP wafer 150 oriented in the (100) plane having a major flat 152 and a minor flat 154 perpendicular to the major flat 152, and a graph 160 of preferred directions of the wafer 100. For orientation, a graph 162 illustrates an [011] axis 164 and a [011] axis 166 relative to the InP wafer 510 and the flats 152, 154. Of note, the terms axis and direction may be used interchangeably herein. Also, the InP wafer 150 can be on the wafer 100. Note the locations of the major and minor flats follow one common convention but others may exist.

[0058] For InP wafers 150 oriented on the (100) plane (the wafer 100), for example, growth enhancement passes through a null when an SAE mask 102 edge is aligned with one of the angles (preferred angles) below relative to the [011] direction 164, collected into two series.

TABLE-US-00001 Series 1: 34 degrees 124 degrees 214 degrees 304 degrees

TABLE-US-00002 Series 2: 56 degrees 146 degrees 236 degrees 326 degrees

[0059] Each series contains four angular directions, with each direction separated by 90 degrees from the other three in the series. For a (100)-oriented InP wafer 150, there are a total of eight orientations available for enhancement- and defect-free SAE mask 102 edges. Specifically, the graph 160 illustrates series 1, 2 in a graph format relative to the [011] direction 164. Note, while the angles in the series 1, 2 are specified relative to the [011] direction 164, those skilled in the art will appreciate these angles for the mask 102 edges could also be specified relative to any direction, including the [011] direction 166, as well as other crystallographic axes not illustrated herein. Also, note, those of ordinary skill in the art will recognize these angles are approximate values.

[0060] FIG. 14 is a diagram of a rectangular mask 102A with an angled orientation according to the series 2 and a zigzag-shaped mask 102B with variable angles from both the series 1, 2. FIG. 15 is a diagram of the InP wafer 150 with an example mask 102A placed thereon. FIG. 16 is a diagram of the InP wafer 150 with an example mask 102B placed thereon. Those of ordinary skill in the art will recognize FIGS. 13-16 are not to scale. Typically, the InP wafer 150 can be on the order of centimeters in size (diameter), from the major flat 152 to the opposite side (top). The masks 102 are sized on the order of hundreds of microns in length and tens of microns in width, with the teeth of the zig-zag on the order of microns.

[0061] The use of the mask 102 with the InP wafer 150 is utilized to form a semiconductor device with SAE, fabricated via a process of growing an epitaxial layer onto a semiconductor wafer 150. In an embodiment, the semiconductor device includes 1) a first area covered by the mask 102 which inhibits crystal growth on the semiconductor wafer 150 surface, 2) a second area, complementary (adjacent) to the first area and not covered by the mask 102, which allows crystal growth on the semiconductor wafer 150, and 3) a perimeter of the mask 102 enclosing the first area and serving as a boundary between the first area and the second area, wherein most of the length of the perimeter is substantially aligned along a preferred crystal direction that provides reduced growth enhancement on the semiconductor wafer 150.

[0062] Also, the semiconductor wafer 150 can have portions where growth enhancement is desired and portions where growth enhancement is not desired, and this disclosure provides a degree of freedom to meet both needs. For example, enhanced growth can be desired for a spot-size converter, and minimal growth can be desired for a traveling-wave electrode.

[0063] In an embodiment, the mask 102A is in the shape of a quadrilateral, namely a polygon with four edges (or sides) and four vertices or corners. That is, the perimeter can be the quadrilateral. The key is that any of the four sides fall in line with the preferred angles.

[0064] In another embodiment, the mask 102B is in the shape of a series of zigzag patterns, namely the perimeter includes a series of small corners that fall in line with the preferred angles.

[0065] The semiconductor wafer surface 150 is composed of a compound of group III and group V elements. In an embodiment, the semiconductor wafer surface 150 is InP cut near the (100) orientation. The preferred crystal direction is one or more of the following angles relative to the [011] direction, in approximate degrees: 34, 124, 214, 304, 56, 146, 236, 326. Note, each of the last four numbers is (360one of the first four numbers) and vice versa, i.e., 326=36034; 236=360124, etc.

[0066] FIG. 17 is a flowchart of a process 180 of growing an epitaxial layer onto a semiconductor wafer for a semiconductor device. The process 180 includes, with a semiconductor wafer having an orientation in a plane, depositing one or more masks to the semiconductor wafer depositing one or more masks to the semiconductor wafer, wherein each mask is configured to cover a portion of the semiconductor wafer, and wherein each mask includes a perimeter having multiple sides that are substantially aligned along a preferred crystal direction relative to the orientation that provides enhanced or reduced growth enhancement at edges of the substantially aligned sides (step 184); and performing Selective Area Epitaxy (SAE) growth on a surface of the semiconductor wafer, (step 186).

[0067] The perimeter can have a shape of a quadrilateral or a series of zigzag patterns. The semiconductor wafer can include a compound of group III and group V elements. The semiconductor wafer can be Indium Phosphide (InP), and the plane can be near a (100) orientation. The preferred crystal direction can be one or more of angles having approximate degrees of 34, 124, 214, 304, 56, 146, 236, and 326, relative to a [011] direction of the semiconductor wafer.

[0068] In an embodiment, a mask is for a spot size converter, and the preferred crystal direction is selected to provide the maximum growth enhancement. In another embodiment, a mask is for a traveling-wave electrode, and the preferred crystal direction is selected to provide the reduced growth enhancement.

[0069] Also, a semiconductor device can be formed by the process 180.

[0070] In another embodiment, a semiconductor device, for fabrication via a process of growing an epitaxial layer onto a semiconductor wafer via Selective Area Epitaxy (SAE), includes a first area covered by a mask which inhibits crystal growth on a surface of the first area; a second area, adjacent to the first area and not covered by a mask, which allows crystal growth on a surface of the second area; and a perimeter of the mask serving as a boundary between the first area and the second area, wherein multiple sides of the perimeter are substantially aligned along a preferred crystal direction relative to an orientation of the semiconductor wafer, to minimize or maximize growth enhancement at edges of the substantially aligned sides.

[0071] FIG. 18 is a photograph of a circular mask within a high-resolution Field of View (FOV), to illustrate how the preferred angles were determined. Of note, the circular mask represents all possible angle values (0 to 360 degrees) relative to the [011] direction 164. With this approach, it was possible to isolate small islands and extract data. It was determined that it is possible to correlate the island height and volume in relation to the angle. In this manner, it was determined that the preferred crystal direction is one or more of the following angles relative to the [011] direction of the InP wafer 150, in approximate degrees: 34, 124, 214, 304, 56, 146, 236, 326. Those skilled in the art will recognize this same approach, namely using a circular mask to experimentally determine growth properties at different angles, could be used on other types of wafers 100, with other crystallographic axes, etc. to determine preferred mask 102 angles.

[0072] Although the present disclosure has been illustrated and described herein with reference to preferred embodiments and specific examples thereof, it will be readily apparent to those of ordinary skill in the art that other embodiments and examples may perform similar functions and/or achieve like results. All such equivalent embodiments and examples are within the spirit and scope of the present disclosure, are contemplated thereby, and are intended to be covered by the following claims.