Patent classifications
B81C2201/0132
MEMS DEVICE WITH INTEGRATED CMOS CIRCUIT
A method of manufacturing a MEMS device, the MEMS device comprising a movable Micro-Electro-Mechanical piezoelectric component and a CMOS circuit configured to be in conductive communication with the Micro-Electro-Mechanical component. A plurality of CMOS circuit layers are formed on a substrate to form the CMOS circuit, the plurality of CMOS circuit layers comprising a plurality of CMOS passivation and metallisation layers. A portion of at least one of the plurality of CMOS passivation and metallisation layers is removed in a component region of the device. One or more component region layers are formed in place of the removed portion in the component region to form the movable Micro-Electro-Mechanical piezoelectric component. The one or more component region layers are different from the portion of the at least one of the plurality of CMOS passivation and metallisation layers.
Calcite channel structures with heterogeneous wettability
A method of making a portion of a microfluidic channel includes lithographically patterning a first pattern into a first layer of photoresist disposed on a substrate, the first pattern representative of morphology of a reservoir rock; etching the first pattern into the substrate to form a patterned substrate; disposing a second layer of photoresist onto the patterned substrate; lithographically patterning a second pattern into the second layer of photoresist to reveal portions of the patterned substrate; and depositing calcite onto the exposed portions of the patterned substrate.
Method and Structure for CMOS-MEMS Thin Film Encapsulation
Representative methods for sealing MEMS devices include depositing insulating material over a substrate, forming conductive vias in a first set of layers of the insulating material, and forming metal structures in a second set of layers of the insulating material. The first and second sets of layers are interleaved in alternation. A dummy insulating layer is provided as an upper-most layer of the first set of layers. Portions of the first and second set of layers are etched to form void regions in the insulating material. A conductive pad is formed on and in a top surface of the insulating material. The void regions are sealed with an encapsulating structure. At least a portion of the encapsulating structure is laterally adjacent the dummy insulating layer, and above a top surface of the conductive pad. An etch is performed to remove at least a portion of the dummy insulating layer.
Deep reactive ion etching process for fluid ejection heads
An ejection head chip and method for a fluid ejection device and a method for reducing a silicon shelf width between a fluid supply via and a fluid ejector stack. The ejection head chip includes a silicon substrate and a fluid ejector stack deposited on the silicon substrate, wherein at least one metal layer of the fluid ejector stack is isolated from a fluid supply via etched in the ejection head chip by an encapsulating material.
Method for preparing micro-cavity array surface product with inclined smooth bottom surface based on air molding method
The present invention provides a method for preparing a micro-cavity array surface with an inclined smooth bottom surface based on an air molding method. The method includes: preparing a micro-cavity array surface; preparing an auxiliary microstructure polymer template, and performing plasma treatment on the auxiliary microstructure polymer template; uniformly spreading a layer of a liquid polymer film to be formed on the auxiliary microstructure polymer template subjected to the plasma treatment; placing a gap bead in an empty position on the micro-cavity array surface; placing the auxiliary microstructure polymer template spread with the liquid polymer film on the gap bead on the micro-cavity array surface, maintaining this state, and feeding the auxiliary microstructure polymer template into a vacuum drying oven; and heating and solidifying the liquid polymer film, and separating the micro-cavity array surface to obtain the micro-cavity array surface with the inclined smooth bottom surface.
FORMATION OF ANTIREFLECTIVE SURFACES
Methods for etching nanostructures in a substrate include depositing a patterned block copolymer on the substrate, the patterned block copolymer including first and second polymer block domains, applying a precursor to the patterned block copolymer to generate an infiltrated block copolymer, the precursor infiltrating into the first polymer block domain and generating a material in the first polymer block domain, applying a removal agent to the infiltrated block copolymer to generate a patterned material, the removal agent removing the first and second polymer block domains from the substrate, and etching the substrate, the patterned material on the substrate masking the substrate to pattern the etching. The etching may be performed under conditions to produce nanostructures in the substrate.
MICRO-ELECTRO-MECHANICAL SYSTEM (MEMS) DEVICE and fabrication method thereof
A micro-electro-mechanical system (MEMS) device includes a supporting substrate, a cavity, a stopper, a MEMS structure, and a bonding dielectric layer. The cavity is located at a top surface of the supporting substrate. The stopper is adjacent to the cavity, where a top surface of the stopper and the top surface of the supporting substrate are on the same level in a height. The MEMS structure is disposed on the supporting substrate, where the MEMS structure includes a proof mass and a suspension beam. The proof mass is disposed directly above the stopper, and the suspension beam is disposed directly above the cavity. The bonding dielectric layer is disposed between the top surface of the supporting substrate and a bottom surface of the MEMS structure.
PACKAGING METHOD AND ASSOCIATED PACKAGING STRUCTURE
The present disclosure provides a packaging method, including: providing a first semiconductor substrate; forming a bonding region on the first semiconductor substrate, wherein the bonding region of the first semiconductor substrate includes a first bonding metal layer and a second bonding metal layer; providing a second semiconductor substrate having a bonding region, wherein the bonding region of the second semiconductor substrate includes a third bonding layer; and bonding the first semiconductor substrate to the second semiconductor substrate by bringing the bonding region of the first semiconductor substrate in contact with the bonding region of the second semiconductor substrate; wherein the first and third bonding metal layers include copper (Cu), and the second bonding metal layer includes Tin (Sn). An associated packaging structure is also disclosed.
Capacitive microphone with well-controlled undercut structure
The present invention provides a MEMS microphone comprising (i) a substrate layer, (ii) a fixed backplate, and (iii) an intermediate layer sandwiched between the substrate layer and the fixed backplate. The substrate layer has a first opening through the thickness of the substrate layer. The intermediate layer has a second opening through the thickness of the intermediate layer. The fixed backplate forms a ceiling of the second opening, and the second opening is larger than the first opening and extends into the first opening, forming a looped recess (“undercut”). The looped recess is defined by a looped ledge on the substrate, a looped sidewall around the second opening, and a looped ceiling from the fixed backplate. The looped sidewall and the looped ceiling are made of a same material.
MEMS DEVICE MANUFACTURING METHOD
The present description concerns a method of manufacturing a microelectromechanical device, including the following successive steps: providing an SOI structure comprising a first semiconductor layer on an insulating layer; forming a second semiconductor layer by epitaxy on top of and in contact with the upper surface of the first semiconductor layer; transferring and bonding, by molecular bonding, a third semiconductor layer onto and in contact with the upper surface of the second semiconductor layer; and forming trenches vertically extending from the upper surface of the third semiconductor layer all the way to the upper surface of the insulating layer, said trenches laterally delimiting a mechanical element of the device.