In a microelectromechanical component according to the invention, at least one microelectromechanical element (5), electrical contacting elements (3) and an insulation layer (2.2) and thereon a sacrificial layer (2.1) formed with silicon dioxide are formed on a surface of a CMOS circuit substrate (1) and the microelectromechanical element (5) is arranged freely movably in at least a degree of freedom. At the outer edge of the microelectromechanical component, extending radially around all the elements of the CMOS circuit, a gas- and/or fluid-tight closed layer (4) which is resistant to hydrofluoric acid and is formed with silicon, germanium or aluminum oxide is formed on the surface of the CMOS circuit substrate (1).

A method includes attaching an upper substrate to an upper surface of a sensor substrate, forming, on an upper surface of the upper substrate, a mask providing a first opening and a second opening communicating with the first opening, the second opening having a width that decreases with increase in a distance from the first opening, carrying out a sandblast process on the upper substrate exposed to an outside via the first opening and the second opening, allowing the sensor substrate to be exposed to the outside immediately below the first opening, and forming a slope on the upper substrate immediately below the second opening, and forming a first wiring member in contact with the exposed sensor substrate and a second wiring member being in contact with the slope and continuing to the first wiring member.

A method includes producing a semiconductor wafer. The semiconductor wafer includes a plurality of microelectromechanical system (MEMS) semiconductor chips, wherein the MEMS semiconductor chips have MEMS structures arranged at a first main surface of the semiconductor wafer, a first semiconductor material layer arranged at the first main surface, and a second semiconductor material layer arranged under the first semiconductor material layer, wherein a doping of the first semiconductor material layer is greater than a doping of the second semiconductor material layer. The method further includes removing the first semiconductor material layer in a region between adjacent MEMS semiconductor chips. The method further includes applying a stealth dicing process from the first main surface of the semiconductor wafer and between the adjacent MEMS semiconductor chips.

A thin film structure (e.g., a near-field transducer), includes a first surface parallel to a substrate on which the thin film structure is deposited and two other surfaces orthogonal to the first surface. The first surface and the two other surfaces have respective first, second, and third selected plane orientations with respective first, second, and third atomic packing factors. The first, second, and third selected plane orientations are selected to maximize an average of the first, second, and third atomic packing factors.

A sensor includes a sensor substrate, and an upper lid substrate joined to an upper surface of the sensor substrate. The sensor substrate includes a fixed part, a deformable beam connected to the fixed part, and a weight connected to the beam. The weight is movable relative to the fixed part. The upper lid substrate includes a first part containing silicon and a second part joined to the first part and containing glass. The first part includes a projection protruding toward the sensor substrate relative to the second part. The sensor has high accuracy or high reliability.

A method for manufacturing a micromechanical sensor, including the steps: providing a MEMS wafer that includes a MEMS substrate, a defined number of etching trenches being formed in the MEMS substrate in a diaphragm area, the diaphragm area being formed in a first silicon layer that is situated at a defined distance from the MEMS substrate; providing a cap wafer; bonding the MEMS wafer to the cap wafer; and forming a media access point to the diaphragm area by grinding the MEMS substrate.

A method for fabricating a microfluidic device includes providing an assembly that includes a first silicon substrate having a hydrophilic silicon oxide top surface that includes a microfluidic channel and a second silicon substrate having a hydrophilic silicon oxide bottom surface directly bonded on the top surface of the first silicon substrate, the second silicon substrate including fluidic access holes giving fluidic access to the microfluidic channel. The method also includes exposing the assembly to oxidative species including one or more oxygen atoms and to heat so as to form silicon oxide at a surface of the access holes and of the microfluidic channel.

The present disclosure provides a method for processing a conductive structure. The method includes the following steps of: forming on a first surface a groove concave from the first surface towards a second surface by means of dry etching; extending the groove from the second surface to form a via through a silicon base; and processing a conductive structure within the via. The method can be applied to a silicon base having a thickness larger than 300 μm. It breaks the limit on thickness that can be processed in the related art and is capable of providing electrical connectivity on both sides of a silicon base. The method is simple and highly reliable, has high processing efficiency and is applicable to mechanized production.

A hardmask composition may include graphene nanoparticles having a size in a range of about 5 nm to about 100 nm and a solvent.

The present disclosure provides a packaging method, including: providing a first semiconductor substrate; forming a bonding region on the first semiconductor substrate, wherein the bonding region of the first semiconductor substrate includes a first bonding metal layer and a second bonding metal layer; providing a second semiconductor substrate having a bonding region, wherein the bonding region of the second semiconductor substrate includes a third bonding layer; and bonding the first semiconductor substrate to the second semiconductor substrate by bringing the bonding region of the first semiconductor substrate in contact with the bonding region of the second semiconductor substrate; wherein the first and third bonding metal layers include copper (Cu), and the second bonding metal layer includes Tin (Sn). An associated packaging structure is also disclosed.