Patent classifications
C30B15/20
METHOD FOR PRODUCING SILICON INGOT SINGLE CRYSTAL
A method for producing Si ingot single crystal including a Si ingot single crystal growing step, a temperature gradient controlling step and a continuous growing step is provided. In the growing step, the Si ingot single crystal is grown in silicon melt in crucible, and the growing step includes providing a low-temperature region in the Si melt and providing a silicon seed to contact the melt surface of the silicon melt to start crystal growth, and silicon single crystal grows along the melt surface of the silicon melt and toward the inside of the silicon melt. In the temperature gradient controlling step, the under-surface temperature gradient of the silicon single crystal is G1, the above-surface temperature gradient of the silicon single crystal is G2, G1 and G2 satisfy: G2/G1<6. The step of controlling the temperature gradient of silicon single crystal is repeated to obtain the Si ingot single crystal.
Method and System for Controlling Temperature during Crystal Growth
The disclosure discloses a method and a system for controlling temperature during crystal growth. The method includes that: the power of each of the heaters is constantly adjusted and simulating is performed by software to calculate the thermal field correspondingly at a solid-liquid interface and vicinity of the solid-liquid interface; the thermal field is coupled with a moving grid to determine whether the solid-liquid interface and the total thermal energy both reach thermal equilibrium; the power of each of the heaters that enables both the solid-liquid interface and the total thermal energy to reach the thermal equilibrium is stored and a thermal equilibrium diagram is drawn based on the power of each of the heaters; and during crystal growth, the power of each of the heaters is selected from the thermal equilibrium diagram which is drawn to control the temperature gradient at the solid-liquid interface.
MODELING THERMAL DONOR FORMATION AND TARGET RESISTIVITY FOR SINGLE CRYSTAL SILICON INGOT PRODUCTION
Methods for producing single crystal silicon ingots are disclosed. The methods may involve modeling formation of thermal donors and target resistivity during downstream annealing processes such as during subsequent device manufacturing such as manufacturing of interposer devices. The model may output a pre-anneal wafer resistivity target range. The single crystal silicon ingot production process may be modeled to determine a counter-doping schedule to achieve the pre-anneal wafer resistivity target range across a longer length of the main body of the ingot.
MODELING THERMAL DONOR FORMATION AND TARGET RESISTIVITY FOR SINGLE CRYSTAL SILICON INGOT PRODUCTION
Methods for producing single crystal silicon ingots are disclosed. The methods may involve modeling formation of thermal donors and target resistivity during downstream annealing processes such as during subsequent device manufacturing such as manufacturing of interposer devices. The model may output a pre-anneal wafer resistivity target range. The single crystal silicon ingot production process may be modeled to determine a counter-doping schedule to achieve the pre-anneal wafer resistivity target range across a longer length of the main body of the ingot.
METHOD OF DETECTING CRYSTALLOGRAPHIC DEFECTS AND METHOD OF GROWING AN INGOT
The invention provides a method of detecting crystallographic defects, comprising: sampling wafer of an ingot in complying with a predetermined wafer sampling frequency; identifying crystallographic defects of the wafer to show the crystallographic defects of the wafer; characterizing observation of the crystallographic defects of the wafer and extracting a value characterizing the crystallographic defects; through a result of characterizing the crystallographic defects, obtaining a radial distribution of density of the wafer and categorizing the crystallographic defects; and obtaining an isogram of the crystallographic defects of the wafer to show a crystallographic defect distribution of the whole ingot according to the value characterizing the crystallographic defects and categories of the crystallographic defects. It is no need to break the ingot to obtain the crystallographic defect distribution of the whole ingot, through which the technology for growing the ingot may be effectively adjusted to obtain the ingot with required characteristics of defect.
Method and apparatus of monocrystal growth
The present invention provides a method and an apparatus of monocrystal growth. The method comprises providing an apparatus comprising a crucible, a first lifting device for lifting the crucible, a deflector tube and a second lifting device for lifting the deflector tube; setting a theoretical distance between the deflector tube and the melt surface, determining a theoretical ratio of the crucible lifting rate relative to the monocrystal lifting rate based on sizes of the crucible and the monocrystal, and starting to grow the monocrystal. During the growth, the position of one or more of the crucible, the deflector tube and the monocrystal is adjusted, the actual distance between the deflector tube and the melt surface is real-time detected, the deviation value between the theoretical and the actual distances is calculated, a variation of the ratio is obtained by the deviation value, and the theoretical ratio is adjusted based on the variation. Based on the variation of the ratio of the crucible lifting rate relative to the monocrystal lifting rate, the speeds of the lifting devices are adjusted to maintain the process lifting rate during the crystal growth without change. The process lifting rate is the lifting rate of the monocrystal ingot relative to the melt surface. The present invention can facilitate to produce the monocrystal with high quality.
Method and apparatus of monocrystal growth
The present invention provides a method and an apparatus of monocrystal growth. The method comprises providing an apparatus comprising a crucible, a first lifting device for lifting the crucible, a deflector tube and a second lifting device for lifting the deflector tube; setting a theoretical distance between the deflector tube and the melt surface, determining a theoretical ratio of the crucible lifting rate relative to the monocrystal lifting rate based on sizes of the crucible and the monocrystal, and starting to grow the monocrystal. During the growth, the position of one or more of the crucible, the deflector tube and the monocrystal is adjusted, the actual distance between the deflector tube and the melt surface is real-time detected, the deviation value between the theoretical and the actual distances is calculated, a variation of the ratio is obtained by the deviation value, and the theoretical ratio is adjusted based on the variation. Based on the variation of the ratio of the crucible lifting rate relative to the monocrystal lifting rate, the speeds of the lifting devices are adjusted to maintain the process lifting rate during the crystal growth without change. The process lifting rate is the lifting rate of the monocrystal ingot relative to the melt surface. The present invention can facilitate to produce the monocrystal with high quality.
GALLIUM-SUBSTITUTED SOLID ELECTROLYTE MATERIAL, AND ALL-SOLID-STATE LITHIUM ION SECONDARY BATTERY
Provided is a novel solid electrolyte material of high density and high ionic conductivity, and an all-solid-state lithium ion secondary battery that utilizes the solid electrolyte material. The solid electrolyte material has a chemical composition represented by Li.sub.7-3xGa.sub.xLa.sub.3Zr.sub.2O.sub.12 (0.08≤x<0.5), has a relative density of 99% or higher, belongs to space group I-43d, in the cubic system, and has a garnet-type structure. The lithium ion conductivity of the solid electrolyte material is 2.0×10.sup.−3 S/cm or higher. The solid electrolyte material has a lattice constant a such that 1.29 nm≤a≤1.30 nm, and lithium ions occupy the 12a site, the 12b site and two types of 48e site, and gallium occupies the 12a site and the 12b site, in the crystal structure. The all-solid-state lithium ion secondary battery has a positive electrode, a negative electrode, and a solid electrolyte. The solid electrolyte is made up of the solid electrolyte material of the present invention.
GALLIUM-SUBSTITUTED SOLID ELECTROLYTE MATERIAL, AND ALL-SOLID-STATE LITHIUM ION SECONDARY BATTERY
Provided is a novel solid electrolyte material of high density and high ionic conductivity, and an all-solid-state lithium ion secondary battery that utilizes the solid electrolyte material. The solid electrolyte material has a chemical composition represented by Li.sub.7-3xGa.sub.xLa.sub.3Zr.sub.2O.sub.12 (0.08≤x<0.5), has a relative density of 99% or higher, belongs to space group I-43d, in the cubic system, and has a garnet-type structure. The lithium ion conductivity of the solid electrolyte material is 2.0×10.sup.−3 S/cm or higher. The solid electrolyte material has a lattice constant a such that 1.29 nm≤a≤1.30 nm, and lithium ions occupy the 12a site, the 12b site and two types of 48e site, and gallium occupies the 12a site and the 12b site, in the crystal structure. The all-solid-state lithium ion secondary battery has a positive electrode, a negative electrode, and a solid electrolyte. The solid electrolyte is made up of the solid electrolyte material of the present invention.
Semiconductor wafer of monocrystalline silicon and method of producing the semiconductor wafer
Epitaxially coated semiconductor wafers of monocrystalline silicon comprise a p.sup.+-doped substrate wafer and a p-doped epitaxial layer of monocrystalline silicon which covers an upper side face of the substrate wafer; an oxygen concentration of the substrate wafer of not less than 5.3×10.sup.17 atoms/cm.sup.3 and not more than 6.0×10.sup.17 atoms/cm.sup.3; a resistivity of the substrate wafer of not less than 5 mΩcm and not more than 10 mΩcm; and the potential of the substrate wafer to form BMDs as a result of a heat treatment of the epitaxially coated semiconductor wafer, where a high density of BMDs has a maximum close to the surface of the substrate wafer.