A method evaluates a defect region of a semiconductor substrate based on C-V characteristics of a MOS structure formed on the semiconductor substrate, including determining a relationship between defect region and flat band voltage or fixed charge density by using a semiconductor substrate having a known defect region, under a heat treatment condition and a C-V characteristic evaluating condition identical to conditions for evaluating a defect region of a semiconductor substrate to be evaluated, determining a flat band voltage or a fixed charge density of the semiconductor substrate to be evaluated from C-V characteristics of a MOS structure formed on the semiconductor substrate to be evaluated, and identifying the defect region of the semiconductor substrate to be evaluated based on the relationship between defect region and flat band voltage or fixed charge density previously determined, whereby the defect region of the semiconductor substrate is evaluated.

The present invention relates to a silicon carbide substrate for use as a crystal seed, comprising a monocrystalline silicon carbide disk covered with a protective oxide layer. The protective oxide layer is intended to be removed to expose an ideal, clean surface of the monocrystalline silicon carbide disk. The present invention also relates to a method of producing at least one bulk silicon carbide single-crystal by sublimation growth using the silicon carbide substrate with protective oxide layer as a seed crystal. The protective oxide layer is removed from the seed crystal surface to expose the underlying monocrystalline silicon carbide disk by a back-etching process performed in-situ in the crystal growth crucible, i.e. after the seed crystal is arranged inside the growth crucible and before the sublimation deposition on the growth surface starts.

Provided is a superlattice structure in which a first crystal layer having a unit lattice of Ca.sub.2Fe.sub.2O.sub.5 with a brownmillerite structure and a second crystal layer having a unit lattice of CaCuO.sub.2 with an infinite layer structure are alternately stacked. The thickness of the first crystal layer is a critical film thickness at which the first crystal layer is able to coherently grow on the second crystal layer. In this superlattice structure, the first crystal layer as the lowermost layer is formed on and in contact with a single crystal substrate, and the second crystal layer and the first crystal layer are alternately stacked on the first crystal layer formed on and in contact with the single crystal substrate.

A method for a heat treatment of a silicon single crystal wafer in an oxidizing ambient, including: performing the heat treatment based on a condition determined by a tripartite correlation between a heat treatment temperature during the heat treatment, an oxygen concentration in the silicon single crystal wafer before the heat treatment, and a growth condition of a silicon single crystal from which the silicon single crystal wafer is cut out. This provides a method for a heat treatment of a silicon single crystal wafer which can annihilate void defects or micro oxide precipitate nuclei in a silicon single crystal wafer with low cost, efficiently, and securely by a heat treatment in an oxidizing ambient.

A method for a heat treatment of a silicon single crystal wafer in an oxidizing ambient, including: performing the heat treatment based on a condition determined by a tripartite correlation between a heat treatment temperature during the heat treatment, an oxygen concentration in the silicon single crystal wafer before the heat treatment, and a growth condition of a silicon single crystal from which the silicon single crystal wafer is cut out. This provides a method for a heat treatment of a silicon single crystal wafer which can annihilate void defects or micro oxide precipitate nuclei in a silicon single crystal wafer with low cost, efficiently, and securely by a heat treatment in an oxidizing ambient.

A method evaluates a defect region of a semiconductor substrate based on C-V characteristics of a MOS structure formed on the semiconductor substrate, including determining a relationship between defect region and flat band voltage or fixed charge density by using a semiconductor substrate having a known defect region, under a heat treatment condition and a C-V characteristic evaluating condition identical to conditions for evaluating a defect region of a semiconductor substrate to be evaluated, determining a flat band voltage or a fixed charge density of the semiconductor substrate to be evaluated from C-V characteristics of a MOS structure formed on the semiconductor substrate to be evaluated, and identifying the defect region of the semiconductor substrate to be evaluated based on the relationship between defect region and flat band voltage or fixed charge density previously determined, whereby the defect region of the semiconductor substrate is evaluated.

A method, for manufacturing a silicon carbide semiconductor device, includes: forming a silicon carbide epitaxial film on a silicon carbide substrate; flattening a surface of the epitaxial film by using chemical mechanical polishing such that the surface of the epitaxial film has an arithmetic mean roughness Ra of 0.3 nm or less; thermally oxidizing the surface of the epitaxial film to form a sacrificial oxide; removing the sacrificial oxide; and cleaning, by using deionized water, a surface of the epitaxial film exposed by the removing of the sacrificial oxide.

A method for a heat treatment of a silicon single crystal wafer in an oxidizing ambient, including: performing the heat treatment based on a condition determined by a tripartite correlation between a heat treatment temperature during the heat treatment, an oxygen concentration in the silicon single crystal wafer before the heat treatment, and a growth condition of a silicon single crystal from which the silicon single crystal wafer is cut out. This provides a method for a heat treatment of a silicon single crystal wafer which can annihilate void defects or micro oxide precipitate nuclei in a silicon single crystal wafer with low cost, efficiently, and securely by a heat treatment in an oxidizing ambient.

We describe herein biocompatible single crystal Cu-based shape memory alloys (SMAs). In particular, we show biocompatibility based on MEM elution cell cytotoxicity, ISO intramuscular implant, and hemo-compatibility tests producing negative cytotoxic results. This biocompatibility may be attributed to the formation of a durable oxide surface layer analogous to the titanium oxide layer that inhibits body fluid reaction to titanium nickel alloys, and/or the non-existence of crystal domain boundaries may inhibit corrosive chemical attack. Methods for controlling the formation of the protective aluminum oxide layer are also described, as are devices including such biocompatible single crystal copper-based SMAs.

Since a high temperature process is required when adding impurities to a semiconductor crystal film by means of ion implantation or by means of thermal diffusion, it has been difficult to form a steep impurity profile. A production method for a single crystal semiconductor film by means of crystal growth using a magnetron sputtering device to which one or more group 14 semiconductor targets are attached, the method being characterized in that at least one of the targets is doped with impurities, the film-forming temperature is 300 C. or higher, the growth rate is 10 nm or less per minute, the sputtering gas is an inert gas, and the one or more targets are sputtered simultaneously.