B01J2219/00504

Integrated circuit with sequentially-coupled charge storage and associated techniques comprising a photodetection region and charge storage regions to induce an intrinsic electric field

Described herein are techniques that improve the collection and readout of charge carriers in an integrated circuit. Some aspects of the present disclosure relate to integrated circuits having pixels with a plurality of charge storage regions. Some aspects of the present disclosure relate to integrated circuits configured to substantially simultaneously collect and read out charge carriers, at least in part. Some aspects of the present disclosure relate to integrated circuits having a plurality of pixels configured to transfer charge carriers between charge storage regions within each pixel substantially at the same time. Some aspects of the present disclosure relate to integrated circuits having three or more sequentially coupled charge storage regions. Some aspects of the present disclosure relate to integrated circuits capable of increased charge transfer rates. Some aspects of the present disclosure relate to techniques for manufacturing and operating integrated circuits according to the other techniques described herein.

Versatile method for the detection of marker-free precision genome editing and genetic variation

The present disclosure provides, inter alia, specially designed DNA adaptors and methods of preparing the same. Methods and kits for carrying out and detecting marker-free precision genome editing and genetic variation using such adaptors are also provided.

INTEGRATED CIRCUIT WITH SEQUENTIALLY-COUPLED CHARGE STORAGE AND ASSOCIATED TECHNIQUES
20220128403 · 2022-04-28 ·

Described herein are techniques that improve the collection and readout of charge carriers in an integrated circuit. Some aspects of the present disclosure relate to integrated circuits having pixels with a plurality of charge storage regions. Some aspects of the present disclosure relate to integrated circuits configured to substantially simultaneously collect and read out charge carriers, at least in part. Some aspects of the present disclosure relate to integrated circuits having a plurality of pixels configured to transfer charge carriers between charge storage regions within each pixel substantially at the same time. Some aspects of the present disclosure relate to integrated circuits having three or more sequentially coupled charge storage regions. Some aspects of the present disclosure relate to integrated circuits capable of increased charge transfer rates. Some aspects of the present disclosure relate to techniques for manufacturing and operating integrated circuits according to the other techniques described herein.

SUBSTRATES, SYSTEMS, AND METHODS FOR NUCLEIC ACID ARRAY SYNTHESIS
20230294064 · 2023-09-21 ·

Disclosed herein are formulations, substrates, and arrays for the synthesis of PNA chains and PNA-DNA chimera on microarrays. In some embodiments, the formulations include a photo-protective compound that shields any PNA monomers, PNA polymers, or PNA-DNA chimera already attached to a microarray from radiation exposure during the synthesis of the PNA or PNA-DNA chains. In some embodiments, substrates and arrays comprise a porous or a planar layer for synthesis and attachment of PNA or DNA monomers, or PNA or PNA-DNA polymers. In some embodiments, disclosed herein are formulations and methods for high efficiency coupling of PNA monomers or PNA polymers to a microarray substrate.

A VERSATILE METHOD FOR THE DETECTION OF MARKER-FREE PRECISION GENOME EDITING AND GENETIC VARIATION
20230347311 · 2023-11-02 ·

The present disclosure provides, inter alia, specially designed DNA adaptors and methods of preparing the same. Methods and kits for carrying out and detecting marker-free precision genome editing and genetic variation using such adaptors are also provided.

INTEGRATED CIRCUIT WITH SEQUENTIALLY-COUPLED CHARGE STORAGE AND ASSOCIATED TECHNIQUES

Described herein are techniques that improve the collection and readout of charge carriers in an integrated circuit. Some aspects of the present disclosure relate to integrated circuits having pixels with a plurality of charge storage regions. Some aspects of the present disclosure relate to integrated circuits configured to substantially simultaneously collect and read out charge carriers, at least in part. Some aspects of the present disclosure relate to integrated circuits having a plurality of pixels configured to transfer charge carriers between charge storage regions within each pixel substantially at the same time. Some aspects of the present disclosure relate to integrated circuits having three or more sequentially coupled charge storage regions. Some aspects of the present disclosure relate to integrated circuits capable of increased charge transfer rates. Some aspects of the present disclosure relate to techniques for manufacturing and operating integrated circuits according to the other techniques described herein.

INTEGRATED CIRCUIT WITH SEQUENTIALLY-COUPLED CHARGE STORAGE AND ASSOCIATED TECHNIQUES
20220128402 · 2022-04-28 ·

Described herein are techniques that improve the collection and readout of charge carriers in an integrated circuit. Some aspects of the present disclosure relate to integrated circuits having pixels with a plurality of charge storage regions. Some aspects of the present disclosure relate to integrated circuits configured to substantially simultaneously collect and read out charge carriers, at least in part. Some aspects of the present disclosure relate to integrated circuits having a plurality of pixels configured to transfer charge carriers between charge storage regions within each pixel substantially at the same time. Some aspects of the present disclosure relate to integrated circuits having three or more sequentially coupled charge storage regions. Some aspects of the present disclosure relate to integrated circuits capable of increased charge transfer rates. Some aspects of the present disclosure relate to techniques for manufacturing and operating integrated circuits according to the other techniques described herein.

ARRAY OF POLYMERIC HYDROGEL NANOSTRUCTURES AND THEIR USES
20210299629 · 2021-09-30 ·

A method for making a microfluidic device having one or more different patterned polymeric hydrogel nanostructure is provided. The method includes: providing a first substrate having a first patterned array of polymeric hydrogel nanostructures on a first interior surface and a peripheral surface portion; providing a second substrate having a second interior surface and a side wall with an end surface; and bonding the end surface of the second substrate to the peripheral surface portion of the first substrate such that the first and second interior surfaces define a hermetic cavity within the bonded first and second substrate. The microfluidic device can be designed to include a variety of different patterned array of polymeric hydrogel nanostructures depending on the desired application and properties for the device.

VERSATILE METHOD FOR THE DETECTION OF MARKER-FREE PRECISION GENOME EDITING AND GENETIC VARIATION
20210283567 · 2021-09-16 ·

The present disclosure provides, inter alia, specially designed DNA adaptors and methods of preparing the same. Methods and kits for carrying out and detecting marker-free precision genome editing and genetic variation using such adaptors are also provided.

INTEGRATED CIRCUIT WITH SEQUENTIALLY-COUPLED CHARGE STORAGE AND ASSOCIATED TECHNIQUES

Described herein are techniques that improve the collection and readout of charge carriers in an integrated circuit. Some aspects of the present disclosure relate to integrated circuits having pixels with a plurality of charge storage regions. Some aspects of the present disclosure relate to integrated circuits configured to substantially simultaneously collect and read out charge carriers, at least in part. Some aspects of the present disclosure relate to integrated circuits having a plurality of pixels configured to transfer charge carriers between charge storage regions within each pixel substantially at the same time. Some aspects of the present disclosure relate to integrated circuits having three or more sequentially coupled charge storage regions. Some aspects of the present disclosure relate to integrated circuits capable of increased charge transfer rates. Some aspects of the present disclosure relate to techniques for manufacturing and operating integrated circuits according to the other techniques described herein.