A method for processing semiconductor wafers includes obtaining measurement data from a surface of a semiconductor wafer processed by a front-end process tool. The method includes determining a center plane of the wafer based on the measurement data, generating raw shape profiles, and generating ideal shape profiles. The method further includes generating Gapi profiles based on the raw shape profiles and the ideal shape profiles, and calculating a Gapi value of the semiconductor wafer based on the Gapi profiles. The generated Gapi profiles and/or the calculated Gapi value may be used to tune the front-end process tool and/or sort the semiconductor wafer for polishing. Systems include at least a front-end process tool, a flatness measurement tool, and a computing device.

A method for processing semiconductor wafers includes obtaining measurement data of an edge profile of a semiconductor wafer processed by a front-end process tool. The method includes determining an edge profile center point based on the measurement data, generating a raw height profile, and generating an ideal edge profile. The method further includes generating a Gapi edge profile of the semiconductor wafer based on the raw height profile and the ideal edge profile and calculating a Gapi edge value of the semiconductor wafer based on the Gapi edge profile. The generated Gapi edge profile and/or the calculated Gapi edge value may be used to tune the front-end process tool and/or sort the semiconductor wafer for polishing. Systems include at least a front-end process tool, a flatness measurement tool, and a computing device.

The disclosed system may include a slicing component that has a cutting blade. The cutting blade may be configured to cut a semiconductor wafer into multiple wafer strips, where the wafer strips have flat top surfaces and multiple edges. The system may also include a chuck that has rotatable wafer plate strips that are respectively configured to support the wafer strips. The system may further include a pivot arm that rotates the chuck from a cutting position facing the slicing component to a rotated, polishing position that faces a polishing component. As such, an exposed edge of each wafer strip faces the polishing component. The system may also include a polishing component that is configured to polish at least a portion of the exposed edge of each wafer strip that is facing the polishing component. Various other methods, systems, and computer-readable media are also disclosed.

A wafer edge polishing apparatus includes a cleaning mechanism exhibiting a superb effect of cleaning slurry residue adhered on a chuck table. This edge polishing device is provided with: a chuck table which sucks/holds a wafer; a rotation drive mechanism which rotates the chuck table; an edge polishing unit which polishes an edge of the wafer while supplying slurry to the wafer, which is rotating while being sucked/held by the chuck table; and a cleaning unit which removes slurry residue on the chuck table. The cleaning unit includes a cleaning head, and cleans the chuck table through high-pressure cleaning and brush-cleaning by using the cleaning head, wherein the cleaning head is provided with a high-pressure jet nozzle and a brush surrounding the periphery of the high-pressure jet nozzle.

The wafer trimming device includes a chuck table configured to hold a target wafer via suction, thereby fixing the target wafer, a notch trimmer configured to trim a notch of the target wafer, and an edge trimmer configured to trim an edge of the target wafer. The notch trimmer includes a notch trimming blade configured to rotate about a rotation axis perpendicular to a circumferential surface of the target wafer. The edge trimmer includes an edge trimming blade configured to rotate about a rotation axis parallel to the circumferential surface of the target wafer.

Provided are a method of polishing a silicon wafer and a method of producing a silicon wafer which can reduce the formation of step-forming microdefects on a silicon wafer. The method includes: a double-side polishing step of performing polishing on front and back surfaces of a silicon wafer; a notch portion polishing step of performing polishing on a beveled portion of a notch portion of the silicon wafer after the double-side polishing step; a peripheral beveled portion polishing step of performing polishing on the beveled portion on the periphery of the silicon wafer other than the beveled portion of the notch portion after the notch portion polishing step; and a finish polishing step of performing finish polishing on the front surface of the silicon wafer after the peripheral beveled portion polishing step. The notch portion polishing step is performed in a state where the front surface is wet with water.

A polishing apparatus for an outer peripheral portion of a wafer includes: a stage for horizontally holding a disc-shaped wafer; a rotation drive unit for rotating the stage around its center axis as a rotation axis; polishing heads having an inner circumferential surface mounted with polishing pads; and a polishing-head drive mechanism for bringing the polishing pads into contact with the outer peripheral portion of the wafer and sliding the polishing heads in a direction slanted relative to a center axis of the wafer or a vertical direction thereof under application of a predetermined polishing pressure to the outer peripheral portion of the wafer. The inner circumferential surface of each of the polishing heads is mounted with two or more types of the polishing pads having different physical property values in the vertical direction.

The present invention relates to a chamfered silicon carbide substrate which is essentially monocrystalline, and to a corresponding method of chamfering a silicon carbide substrate. A silicon carbide substrate according to the invention comprises a main surface (102), wherein an orientation of said main surface (102) is such that a normal vector ({right arrow over (O)}) of the main surface (102) includes a tilt angle with a normal vector ({right arrow over (N)}) of a basal lattice plane (106) of the substrate, and a chamfered peripheral region (110), wherein a surface of the chamfered peripheral region includes a bevel angle with said main surface, wherein said bevel angle is chosen so that, in more than 75% of the peripheral region, normal vectors ({right arrow over (F)}_i) of the chamfered peripheral region (110) differ from the normal vector of the basal lattice plane by less than a difference between the normal vector of the main surface and the normal vector of the basal lattice plane of the substrate.

A polishing apparatus capable of forming a step-shaped recess having a right-angled cross section in an edge portion of a substrate, such as a wafer, is disclosed. The polishing apparatus includes: a substrate rotating device configured to rotate the substrate about a rotation axis; a first roller having a first circumferential surface configured to press a polishing tape against the edge portion of the substrate; and a second roller having a second circumferential surface in contact with the first circumferential surface. The second roller has a tape stopper surface that restricts movement of the polishing tape in a direction away from the rotation axis. The tape stopper surface is located radially outward of the first circumferential surface.

A method evaluates an edge shape of a silicon wafer, in which as shape parameters in a wafer cross section, when defining a radial direction reference L1, a radial direction reference L2, an intersection point P1, a height reference plane L3, h1 [μm], h2 [μm], a point Px3, a straight line Lx, an angle θx, a point Px0, δ [μm], a point Px1, and a radius Rx [μm], the edge shape of the silicon wafer is measured, values of the shape parameters h1, h2, and δ are set, the shape parameters Rx and θx are calculated in accordance with the definition based on measurement data of the edge shape, and the edge shape of the silicon wafer is determined from the calculated Rx and θx to be evaluated. Consequently, a method evaluates an edge shape of a silicon wafer capable of preventing an occurrence of trouble.