A method and structure for a PLCSP (Package Level Chip Scale Package) MEMS package. The method includes providing a MEMS chip having a CMOS substrate and a MEMS cap housing at least a MEMS device disposed upon the CMOS substrate. The MEMS chip is flipped and oriented on a packaging substrate such that the MEMS cap is disposed above a thinner region of the packaging substrate and the CMOS substrate is bonding to the packaging substrate at a thicker region, wherein bonding regions on each of the substrates are coupled. The device is sawed to form a package-level chip scale MEMS package.

A sensor device includes a sensor element, a substrate, and a bonding wire. Over the substrate, provided is the sensor element. The bonding wire forms at least part of a connection path that electrically connects the sensor element and the substrate together. The bonding wire is provided to connect two connection surfaces that intersect with each other.

A method includes obtaining an active feature layer having a first surface bearing one or more active feature areas. A first capacitor plate of a first capacitor is formed on an interior surface of a cap. A second capacitor plate of the first capacitor is formed on an exterior surface of the cap. The first capacitor plate of the first capacitor overlays and is spaced apart from the second capacitor plate of the first capacitor along a direction that is orthogonal to the exterior surface of the cap to form the first capacitor. The cap is coupled with the first surface of the active feature layer such that the second capacitor plate of the first capacitor is in electrical communication with at least a first active feature of the active feature layer. The cap is bonded with the passive layer substrate.

Representative implementations of techniques and devices provide seals for sealing the joints of bonded microelectronic devices as well as bonded and sealed microelectronic assemblies. Seals are disposed at joined surfaces of stacked dies and wafers to seal the joined surfaces. The seals may be disposed at an exterior periphery of the bonded microelectronic devices or disposed within the periphery using the various techniques.

A method for operating an electronic device comprising a first and second MEMS device and a semiconductor substrate disposed upon a mounting substrate includes subjecting the first MEMS device and the second MEMS device to physical perturbations, wherein the physical perturbations comprise first physical perturbations associated with the first MEMS device and second physical perturbations associated with the second MEMS device, wherein the first physical perturbations and the second physical perturbations are substantially contemporaneous, determining in a plurality of CMOS circuitry formed within the one or more semiconductor substrates, first physical perturbation data from the first MEMS device in response to the first physical perturbations and second physical perturbation data from the second MEMS device in response to the second physical perturbations, determining output data in response to the first physical perturbation data and to the second physical perturbation data, and outputting the output data.

An apparatus and method for wafer-level hermetic packaging of MicroElectroMechanical Systems (MEMS) devices of different shapes and form factors is presented in this disclosure. The method is based on bonding a glass cap wafer with fabricated micro-glassblown “bubble-shaped” structures to the substrate glass/Si wafer. Metal traces fabricated on the substrate wafer serve to transfer signals from the sealed cavity of the bubble to the outside world. Furthermore, the method provides for chip-level packaging of MEMS three dimensional structures. The packaging method utilizes a micro glass-blowing process to create “bubbleshaped” glass lids. This new type of lids is used for vacuum packaging of three dimensional MEMS devices, using a standard commercially available type of package.

A method includes obtaining an active feature layer having a first surface bearing one or more active feature areas. A first capacitor plate of a first capacitor is formed on an interior surface of a cap. A second capacitor plate of the first capacitor is formed on an exterior surface of the cap. The first capacitor plate of the first capacitor overlays and is spaced apart from the second capacitor plate of the first capacitor along a direction that is orthogonal to the exterior surface of the cap to form the first capacitor. The cap is coupled with the first surface of the active feature layer such that the second capacitor plate of the first capacitor is in electrical communication with at least a first active feature of the active feature layer. The cap is bonded with the passive layer substrate.

A microelectromechanical device includes: a body accommodating a microelectromechanical structure; and a cap bonded to the body and electrically coupled to the microelectromechanical structure through conductive bonding regions. The cap including a selection module, which has first selection terminals coupled to the microelectromechanical structure, second selection terminals, and at least one control terminal, and which can be controlled through the control terminal to couple the second selection terminals to respective first selection terminals according, selectively, to one of a plurality of coupling configurations corresponding to respective operating conditions.

An integrated device package is disclosed. The integrated device package can include a packaging structure defining a cavity. An integrated device die can be disposed at least partially within the cavity. A gel can be disposed within the cavity surrounding the integrated device. A portion of the gel can be disposed between a lower surface of the integrated device die and an upper surface of the packaging structure within the cavity.

[Object] To provide an electronic device, a part mounting board, and an electronic apparatus that are capable of preventing warpage of a board from occurring. [Solving Means] An electronic device according to an embodiment of the present technology includes a first circuit board and a second circuit board. The first circuit board includes a first main surface, a second main surface, and a plurality of external terminals. The plurality of external terminals include a first terminal group located at an outermost periphery of the first main surface, and are arranged on the first main surface in a matrix pattern. The second circuit board includes a terminal surface facing the second main surface, and a plurality of connection terminals. The plurality of connection terminals include a second terminal group that is arranged on the terminal surface and faces at least a part of the first terminal group, and are electrically connected to the second main surface.