A semiconductor package device and a method of manufacturing a semiconductor package device are provided. The semiconductor package device includes a substrate, a first electronic component, a first dielectric layer, and a first hole. The substrate has a first surface and a second surface opposite to the first surface. The first electronic component is disposed on the first surface. The first dielectric layer is disposed on the second surface and has a third surface away from the substrate. The first hole extends from the first dielectric layer and the substrate. The first hole is substantially aligned with the first electronic component.

A downhole sensor system includes a first sensor package having a substrate, an integrated circuit chip mounted to the substrate, the integrated circuit chip including a processor, a transducer chip mounted to the integrated circuit chip, and a plurality of sensors configured to measure at least shock, pressure, temperature, and humidity. At least one of the plurality of sensors is mounted to the transducer chip such that a stack is formed at least from the substrate, the integrated circuit, the transducer chip, and the sensor. The plurality of sensors are in communication with the processor.

A die attachment to a support is disclosed. In an embodiment, a semiconductor package includes a support and a die attached to the support by an adhesive on a backside of the die, wherein the die includes a capacitive pressure sensor integrated on a CMOS read-out circuit, and wherein the adhesive covers only a part of the backside of the die.

A semiconductor device may include a first substrate, a first electrical component, a lid, a second substrate, and a second electrical component. The first substrate may include an upper surface, a lower surface, and an upper cavity in the upper surface. The first electrical component may reside in the upper cavity of the first substrate. The lid may cover the upper cavity and may include a port that permits fluid to flow between an environment external to the semiconductor device and the upper cavity. The second substrate may include the second electrical component mounted to an upper surface of the second substrate. The lower surface of the first substrate and the upper surface of the second substrate may fluidically seal the second electrical component from the upper cavity.

A sensor device includes a sensor element, a supporting member, a substrate, and a bonding wire. The supporting member is electrically connected to the sensor element. The substrate is electrically connected to the supporting member. The bonding wire forms at least part of a connection path that electrically connects the sensor element and the supporting member together. The substrate and an installation member on which the sensor element is installed intersect with each other. The sensor element and the supporting member are separated from each other.

In an embodiment, a semiconductor package includes a support and a stack of two or more semiconductor dies, the stack including an upper die and further including a lower die attached to the support by adhesive on a backside of the lower die, wherein the adhesive covers only part of the backside of the lower die, and wherein the adhesive has a plurality of non-contiguous regions on the backside of the lower die.

The present disclosure describes a process for making a three-dimensional (3D) package, which starts with providing a mold precursor module that includes a first device die and a floor connectivity die (FCD) encapsulated by a mold compound. The FCD includes a sacrificial die body and multiple floor interconnections underneath the sacrificial die body. Next, the mold compound is thinned down until the sacrificial die body of the FCD is completely consumed, such that each floor interconnection is exposed through the mold compound. The thinning down step does not affect a device layer in the first device die. A second device die, which includes a die body and multiple electrical die interconnections, is then mounted over the exposed floor interconnections. Herein, each electrical die interconnection is vertically aligned with and electrically connected to a corresponding floor interconnection from the FCD.

An electronic device includes a microelectromechanical system (MEMS) rectifier. The MEMS rectifier includes a mainboard and a sub-board. The mainboard has one or more radiofrequency (RF) inputs configured to receive an RF signal, and a first electrical contact. The sub-board is positioned parallel to the mainboard with a gap in-between, and has a thin film piezoelectric layer, a second electrical contact positioned opposite the first electrical contact, and a ground plane. The sub-board is configured to vibrate as the RF signal is received at the one or more RF inputs, and the thin film piezoelectric layer is configured to generate energy due to the vibration and piezoelectric properties of the thin film piezoelectric layer.

A semiconductor device includes a substrate. A first semiconductor die including a microelectromechanical system (MEMS) is disposed over the substrate. A lid is disposed on the substrate around the first semiconductor die. A first encapsulant is deposited over the substrate and lid. A second encapsulant is deposited into the lid.

A method of making a system-in-package device, and a system-in-package device is disclosed. In the method, at least one first species die with predetermined dimensions, at least one second species die with predetermined dimensions, and at least one further component of the system-in-device is included in the system-in package device. At least one of the first and second species dies is selected for redimensioning, and material is added to at least one side of the selected die such that the added material and the selected die form a redimensioned die structure. A connecting layer is formed on the redimensioned die structure. The redimensioned die structure is dimensioned to allow mounting of the non-selected die and the at least one further component into contact with the redimensioned die structure via the connecting layer.