A semiconductor structure is provided. The semiconductor structure includes a first substrate, a semiconductor layer, a second substrate, and a eutectic sealing structure. The semiconductor layer is over the first substrate. The semiconductor layer has a cavity at least partially through the semiconductor layer. The second substrate is over the semiconductor layer. The second substrate has a through hole. The eutectic sealing structure is on the second substrate and covers the through hole. The eutectic sealing structure comprises a first metal layer and a second metal layer eutectically bonded on the first metal layer. A method for manufacturing a semiconductor structure is also provided.

A method for manufacturing a semiconductor structure is provided. The method includes the operations as follows. A first substrate having a top surface is received. A semiconductor layer is formed over the first substrate. A cavity is formed at the top surface of the semiconductor layer. A second substrate is bonded over the first substrate to cover the semiconductor layer. The second substrate has a through hole connected to the cavity of the semiconductor layer. A eutectic sealing structure is formed on the second substrate to cover the through hole. The eutectic sealing structure includes a first metal layer and a second metal layer eutectically bonded on the first metal layer.

The present disclosure provides a semiconductor structure and a method for fabricating semiconductor structure. The semiconductor structure includes a first device, configured to be a complementary metal oxide semiconductor device, wherein the first device includes a substrate, a multi-layer structure disposed on the substrate, a first hole, defined between a first end with a first circumference and a second end with a second circumference, a second hole, aligned to the first hole and defined between the second end and a third end with a third circumference, wherein the third circumference is larger than the first circumference and the second circumference, and a second device, configured to be a micro-electro mechanical system device and bonded to the first device, wherein a first chamber is between the first device and the second device, and the first end links with the first chamber, and a sealing object configured to seal the second hole.

A semiconductor structure includes: a first device; a second device contacted with the first device, wherein a chamber is formed between the first device and the second device; a first hole disposed in the second device and defined between a first end with a first circumference and a second end with a second circumference; a second hole disposed in the second device and aligned to the first hole; and a sealing object for sealing the second hole. The first end links with the chamber, and the first circumference is different from the second circumference, the second hole is defined between the second end and a third end with a third circumference, and the second circumference and the third circumference are smaller than the first circumference.

Various embodiments of the present disclosure are directed towards a method for manufacturing an integrated chip, the method comprises forming an interconnect structure over a semiconductor substrate. An upper dielectric layer is formed over the interconnect structure. An outgas layer is formed within the upper dielectric layer. The outgas layer comprises a first material that is amorphous. A microelectromechanical systems (MEMS) substrate is formed over the interconnect structure. The MEMS substrate comprises a moveable structure directly over the outgas layer.

A semiconductor layer having an opening and a MEMS resonator formed in the opening is disposed between first and second substrates to encapsulate the MEMS resonator. An electrical contact that extends from the opening to an exterior of the MEMS device is formed at least in part within the semiconductor layer and at least in part within the first substrate.

Various embodiments of the present disclosure are directed towards a method for manufacturing a microelectromechanical systems (MEMS) device. The method includes forming a particle filter layer over a carrier substrate. The particle filter layer is patterned while the particle filter layer is disposed on the carrier substrate to define a particle filter in the particle filter layer. A MEMS substrate is bonded to the carrier substrate. A MEMS structure is formed over the MEMS substrate.

Various embodiments of the present disclosure are directed towards a microphone including a particle filter disposed between a microelectromechanical systems (MEMS) substrate and a carrier substrate. A MEMS device structure overlies the MEMS substrate. The MEMS device structure includes a diaphragm having opposing sidewalls that define a diaphragm opening. The carrier substrate underlies the MEMS substrate. The carrier substrate has opposing sidewalls that define a carrier substrate opening underlying the diaphragm opening. A filter stack is sandwiched between the carrier substrate and the MEMS substrate. The filter stack includes an upper dielectric layer, a lower dielectric layer, and a particle filter layer disposed between the upper and lower dielectric layers. The particle filter layer includes the particle filter spaced laterally between the opposing sidewalls of the carrier substrate.

Various embodiments of the present disclosure are directed towards a microphone including a particle filter disposed between a microelectromechanical systems (MEMS) substrate and a carrier substrate. A MEMS device structure overlies the MEMS substrate. The MEMS device structure includes a diaphragm having opposing sidewalls that define a diaphragm opening. The carrier substrate underlies the MEMS substrate. The carrier substrate has opposing sidewalls that define a carrier substrate opening underlying the diaphragm opening. A filter stack is sandwiched between the carrier substrate and the MEMS substrate. The filter stack includes an upper dielectric layer, a lower dielectric layer, and a particle filter layer disposed between the upper and lower dielectric layers. The particle filter layer includes the particle filter spaced laterally between the opposing sidewalls of the carrier substrate.

Various embodiments of the present disclosure are directed towards an integrated chip including a capping structure over a device substrate. The device substrate includes a first microelectromechanical systems (MEMS) device and a second MEMS device laterally offset from the first MEMS device. The capping structure includes a first cavity overlying the first MEMS device and a second cavity overlying the second MEMS device. The first cavity has a first gas pressure and the second cavity has a second gas pressure different from the first cavity. An outgas layer abutting the first cavity. The outgas layer includes an outgas material having an outgas species. The outgas material is amorphous.