A wafer processing method is disclosed to divide a wafer of glass substrate into individual chips along division lines. In the shield tunnel forming step, a pulsed laser beam of a wavelength, which transmits through the wafer, is irradiated with its focal point positioned at a region corresponding to each division line so that a plurality of shield tunnels which are each formed of perforations and affected regions surrounding the perforations are formed along the division lines, respectively. In the modified layer forming step, another pulsed laser beam of a wavelength, which transmits through the wafer, is irradiated with its focal point positioned at the region corresponding to each division line so that modified layers are formed in addition to the shield tunnels along the division lines, respectively. In the dividing step, an external force is applied to the wafer to divide the wafer into individual chips.

A fabrication method includes arranging a plurality of dice on a substrate and performing a first etching process that etches a first layer of the substrate at a boundary between adjacent dice on the substrate. The etching forms facets of one or more waveguides that are defined within the first layer, and the etching leaves a portion of the first layer in the boundary between the adjacent dice. The method continues with a second etching process that etches the portion of the first layer and a second layer beneath the portion of the first layer, the second etching process forming a trench in the boundary where the second layer has a different material than the first layer. The method also includes separating the dice from one another along the trench.

A method includes producing a semiconductor wafer. The semiconductor wafer includes a plurality of microelectromechanical system (MEMS) semiconductor chips, wherein the MEMS semiconductor chips have MEMS structures arranged at a first main surface of the semiconductor wafer, a first semiconductor material layer arranged at the first main surface, and a second semiconductor material layer arranged under the first semiconductor material layer, wherein a doping of the first semiconductor material layer is greater than a doping of the second semiconductor material layer. The method further includes removing the first semiconductor material layer in a region between adjacent MEMS semiconductor chips. The method further includes applying a stealth dicing process from the first main surface of the semiconductor wafer and between the adjacent MEMS semiconductor chips.

A sensor device package and method of manufacturing the same are provided. The sensor device package includes a carrier, a sensor component, an encapsulation layer and a protection film. The sensor component is disposed on the carrier, and the sensor component includes an upper surface and edges. The encapsulation layer is disposed on the carrier and encapsulates the edges of the sensor component. The protection film covers at least a portion of the upper surface of the sensor component.

A MEMS device and a MEMS device manufacturing method are provided for suppressing damage to device parts. An exemplary method of manufacturing a resonance device includes radiating laser light from a bottom surface side of a second substrate to form modified regions inside the second substrate along dividing lines of a first substrate, which has device parts formed on a top surface thereof, and the second substrate, the top surface of which is bonded to the bottom surface of the first substrate via bonding portions. The method further includes dividing the first and second substrates along the dividing lines by applying stress to the modified regions. The bonding portions are formed along the dividing lines and block the laser light.

A method, system, apparatus, and/or device to creating a set of miniaturized electrode pillars. The method, system, apparatus, and/or device may include patterning a set of miniaturized electrode pillars on a substrate and coating the set of miniaturized electrode pillars with an interstitial filler disposed between the set of miniaturized electrode pillars. The interstitial filler may insulate the set of miniaturized electrode pillars from each other and bolster the set of miniaturized electrode pillars.

A stacked structure includes a polymer layer and a metal layer. The metal layer is disposed on the polymer layer. A burr length on a surface of the polymer layer is about 0.8 m to about 150 m, and a burr length on a surface of the metal layer is about 0.8 m to about 7 m.

A laser micro-machining process called laser-assisted material phase-change and expulsion (LAMPE) micromachining that includes cutting features in a cutting surface of a piece of material using a pulsed laser with intensity, pulse width and pulse rate set to melt and eject liquid material without vaporizing said material, or, in the case of silicon, create an ejectible silicon oxide. Burrs are removed from the cutting surface by electro-polishing the cutting surface with a dilute acid solution using an electric potential higher than a normal electro-polishing electric potential. A multi-lamina assembly of laser-micro-machined laminates (MALL) may utilize MEMS. In the MALL process, first, the individual layers of a micro-electromechanical system (MEMS) are fabricated using the LAMPE micro-machining process. Next, the fabricated microstructure laminates are stack assembled and bonded to fabricate MEM systems. The MALL MEMS fabrication process enables greater material section and integration, greater design flexibility, low-cost manufacturing, rapid development, and integrated packaging.

Process for producing semiconductor devices in a substrate, comprising: photolithography of a pattern of a reticle onto a portion of the substrate, defining first elements of the semiconductor devices, an exposure of the pattern being repeated a plurality of times in order to define all of the devices, photolithography of a pattern of an etch mask over all of the substrate, etching photolithography patterns into one portion of the thickness of the substrate, wherein first dicing lanes encircling the devices are included in the pattern of the etch mask and/or of the reticle, and the photolithography of the etch mask defines second dicing lanes defined by predetermined fracture lines of the edges of the substrate, and furthermore comprising the implementation of a step of irradiating the substrate with a laser beam through the first and second dicing lanes.

An example embodiment may include a method for placing on a carrier substrate a semiconductor device. The method may include providing a semiconductor substrate comprising a rectangular shaped assist chip, which may include at least one semiconductor device surrounded by a metal-free border. The method may also include dicing the semiconductor substrate to singulate the rectangular shaped assist chip. The method may further include providing a carrier substrate having adhesive thereon. The method may additionally include transferring to and placing on the carrier substrate the rectangular shaped assist chip, thereby contacting the adhesive with the rectangular shaped assist chip at least at a location of the semiconductor device. The method may finally include singulating the semiconductor device, while remaining attached to the carrier substrate by the adhesive, by removing a part of rectangular shaped assist chip other than the semiconductor device.