B81C2203/019

Wafer level package for device
20230050181 · 2023-02-16 ·

According to an example aspect of the present invention, there is provided a wafer level package for a device, the package comprising: a first substrate and a second substrate, a sealing structure comprising a seal ring and a bonding layer between the first substrate and the second substrate, and a lateral electrical connection line on a surface of the first substrate, which lateral electrical connection line extends through the seal ring for creating an electrical connection between the device inside the package and an electrical circuit outside the package.

METHOD AND SYSTEM FOR FABRICATING A MEMS DEVICE CAP
20230045563 · 2023-02-09 ·

A device includes a substrate comprising a first standoff, a second standoff, a third standoff, a first cavity, a second cavity, and a bonding material covering a portion of the first, the second, and the third standoff. The first cavity is positioned between the first and the second standoffs, and the second cavity is positioned between the second and the third standoffs. The first cavity comprises a first cavity region and a second cavity region separated by a portion of the substrate extruding thereto, and wherein a depth associated with the first cavity region is greater than a depth associated with the second cavity. A surface of the first cavity is covered with a getter material.

MEMs device and electronic device

An MEMS device includes: a first member; a second member forming a sealed space with the first member therebetween; and a third member disposed between the first member and the second member and joined to the first member and the second member, in which the third member has lower rigidity than rigidity of the first member and the second member, and the third member is provided with a communication portion that establishes communication between the sealed space and an external space.

Pressure sensing implant

A wireless circuit includes a housing having at least one opening, and sensor connected to the housing at the opening. The sensor includes a first layer having a first dimension and a second layer having a second dimension shorter than the first dimension. The second layer may be positioned entirely within the housing and a surface of said first layer may be exposed to an exterior of the housing.

INERTIAL SENSOR, METHOD FOR MANUFACTURING INERTIAL SENSOR, AND INERTIAL MEASUREMENT UNIT
20230221346 · 2023-07-13 ·

An inertial sensor 1 includes: a base body; a lid body facing the base body; a functional element disposed in a cavity between the base body and the lid body and including a semiconductor layer; an adhesive layer disposed in a peripheral region surrounding the cavity and adhering the base body and the lid body to each other; and a sealer configured to seal a hole which communicates the cavity with an outside and which is disposed in the peripheral region. The sealer is provided in contact with the lid body and the base body, and includes a material of the lid body and a material of the adhesive layer.

Method for forming hybrid-bonding structure

A method for forming a hybrid-bonding structure is provided. The method includes forming a first dielectric layer over a first semiconductor substrate. The first semiconductor substrate includes a conductive structure. The method also includes partially removing the first dielectric layer to form a first dielectric dummy pattern, a second dielectric dummy pattern and a third dielectric dummy pattern and an opening through the first dielectric layer. The first dielectric dummy pattern, the second dielectric dummy pattern and the third dielectric dummy pattern are surrounded by the opening. In addition, the method includes forming a first conductive line in the opening. The first conductive line is in contact with the conductive structure.

SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THEREOF
20220411260 · 2022-12-29 ·

A semiconductor structure is provided. The semiconductor structure includes a first substrate, a semiconductor layer, a second substrate, and a eutectic sealing structure. The semiconductor layer is over the first substrate. The semiconductor layer has a cavity at least partially through the semiconductor layer. The second substrate is over the semiconductor layer. The second substrate has a through hole. The eutectic sealing structure is on the second substrate and covers the through hole. The eutectic sealing structure comprises a first metal layer and a second metal layer eutectically bonded on the first metal layer. A method for manufacturing a semiconductor structure is also provided.

Semiconductor device

A semiconductor device may include a first substrate, a first electrical component, a lid, a second substrate, and a second electrical component. The first substrate may include an upper surface, a lower surface, and an upper cavity in the upper surface. The first electrical component may reside in the upper cavity of the first substrate. The lid may cover the upper cavity and may include a port that permits fluid to flow between an environment external to the semiconductor device and the upper cavity. The second substrate may include the second electrical component mounted to an upper surface of the second substrate. The lower surface of the first substrate and the upper surface of the second substrate may fluidically seal the second electrical component from the upper cavity.

Apparatus having a bondline structure and a diffusion barrier with a deformable aperture

In described examples, a bondline structure is arranged along a periphery of a cavity. The bondline structure extends from a first substrate and is configured to bond with an interposer arranged on a second substrate. A diffusion barrier is arranged on the first substrate for contacting the interposer. The diffusion barrier is arranged to impede a contaminant against migrating from the bondline structure and entering the cavity.

WAFER LEVEL PROCESSING FOR MICROELECTRONIC DEVICE PACKAGE WITH CAVITY
20230092132 · 2023-03-23 ·

A described example includes: a MEMS component on a device side surface of a first semiconductor substrate; a second semiconductor substrate bonded to the device side surface of the first semiconductor substrate by a first seal patterned to form sidewalls that surround the MEMS component; a third semiconductor substrate having a second seal extending from a surface and bonded to the backside surface of the first semiconductor substrate by the second seal, the second seal forming sidewalls of a gap beneath the MEMS component. A trench extends through the first semiconductor substrate and at least partially surrounds the MEMS component. The third semiconductor substrate is mounted on a package substrate. A bond wire or ribbon bond couples the bond pad to a conductive lead on the package substrate; and mold compound covers the MEMS component, the bond wire, and a portion of the package substrate.