Embodiments disclosed are systems and methods for fabricating microchannels in metal. In an embodiments, a method includes providing a first metallic plate having a first surface with an elongated slot recessed therein, providing a second metallic plate having a second surface, interfacing the first surface of the first metallic plate with the second surface of the second metallic plate with the second surface covering the elongated slot to form a microchannel between the first metallic plate and the second metallic plate, thermal bonding the first metallic plate to the second metallic plate to form a metallic body having the microchannel extending therethrough, and infiltrating the metallic body with an infiltrant.

The application describes MEMS transducer structures comprising a membrane structure having a flexible membrane layer and at least one electrode layer. The electrode layer is spaced from the flexible membrane layer such that at least one air volume extends between the material of the electrode layer and the membrane layer. The electrode layer is supported relative to the flexible membrane by means of a support structure which extends between the first electrode layer and the flexible membrane layer.

A device includes a first member, a second member, and a bonding layer. A first surface of the first member and a second surface of the second member are bonded to each other via the bonding layer. The bonding layer includes a filler particle configured to be in contact with both of the first surface and the second surface, and a solidified adhesive. A distance between the first surface and the second surface is smaller than a diameter of the filler particle at at least one portion of an outer edge of the bonding layer.

A microchannel chip with which channel deformation does not occur even when high-temperature and high-pressure sterilization treatment is performed and with which strong joining performance of substrates is maintained; and a method for manufacturing the same are provided. A microchannel chip comprising: a channel substrate having a microchannel formed on at least one surface thereof; a lid substrate; and a joining layer joining the channel substrate and the lid substrate, wherein the channel substrate, the lid substrate, and the joining layer are each formed of a cycloolefin polymer, a glass-transition temperature Tg.sub.s1 of a cycloolefin polymer forming the channel substrate, a glass-transition temperature Tg.sub.s2 of a cycloolefin polymer forming the lid substrate, and a glass-transition temperature Tg.sub.2 of a cycloolefin polymer forming the joining layer have relationships: Tg.sub.s1>Tg.sub.2; and Tg.sub.s2>Tg.sub.2, and the joining layer has a thickness within a specific range.

Provided is a microchip that can achieve a favorable bonding state in the bonding portion between first and second substrates even if the microchip is large in size. A microchip includes a first substrate made of a resin and a second substrate made of a resin, the first substrate and the second substrates being bonded to each other, and a channel surrounded by a bonding portion between the first substrate and the second substrate is formed by a channel forming step formed at least in the first substrate. Further, a noncontact portion is formed to surround the bonding portion, and an angle θ.sub.1 formed between a side wall surface of the channel forming step and a bonding surface continuous therewith satisfies θ.sub.1>90°.

A 2-in-1 power electronics assembly includes a frame with a lower dielectric layer, an upper dielectric layer spaced apart from the lower dielectric layer, and a sidewall disposed between and coupled to the lower dielectric layer and the upper dielectric layer. The lower dielectric layer includes a lower cooling fluid inlet and the upper dielectric layer includes an upper cooling fluid outlet. A first semiconductor device assembly and a second semiconductor device assembly are included and disposed within the frame. The first semiconductor device is disposed between a first lower metal inverse opal (MIO) layer and a first upper MIO layer, and the second semiconductor device is disposed between a second lower MIO layer and a second upper MIO layer. An internal cooling structure that includes the MIO layers provides double sided cooling for the first semiconductor device and the second semiconductor device.

A method of manufacturing a semiconductor device includes: forming a first substrate includes a membrane stack over a first dielectric layer, the membrane stack having a first electrode, a second electrode over the first electrode and a piezoelectric layer between the first electrode and the second electrode, a third electrode over the first dielectric layer, and a second dielectric layer over the membrane stack and the third electrode; forming a second substrate, including: a redistribution layer (RDL) over a third substrate, the RDL having a fourth electrode; and a first cavity on a surface of the RDL adjacent to the fourth electrode; forming a second cavity in one of the first substrate and the second substrate; and bonding the first substrate to the second substrate.

A microfluidic device includes a silicon device and a metallic component. The silicon device and the metallic component are attached by preparing a surface of a silicon device to be solderable, preparing a corresponding surface of a metallic component to be solderable, and soldering the prepared surface of the silicon device to the corresponding prepared surface of the metallic component with a solder of a pre-defined composition and thickness to accommodate strain due to co-efficient of thermal expansion (CTE) mismatch between the silicon device and the metallic component.

An encapsulation chip manufacturing method includes forming first and second dicing grooves in a surface of a cap wafer and aligning the cap wafer and a device substrate such that the surface of the cap wafer faces a surface of the device substrate. The device substrate includes a device affixed to the surface and a bond pad on the surface and coupled to the device. The cap wafer is bonded to the device substrate and partially diced at the first and second dicing grooves such that the bond pad is exposed. Aligning the cap wafer and the device substrate includes aligning the first and second dicing grooves between the bond pad and a bonding area at which the cap wafer is bonded to the device substrate. A width of the first and second dicing grooves prevents cap wafer dust formed during the partial dicing from falling on the bond pad.

A system, configured to facilitate processing and detection of nucleic acids, the system comprising a process fluid container and a cartridge comprising: a top layer, a set of sample port-reagent port pairs, a shared fluid port, a vent region, a heating region, and a set of detection chambers; an intermediate substrate, coupled to the top layer comprising a waste chamber; an elastomeric layer, partially situated on the intermediate substrate; and a set of fluidic pathways, each formed by at least a portion of the top layer and a portion of the elastomeric layer, wherein each fluidic pathway is fluidically coupled to a sample port-reagent port pair, the shared fluid port, and a detection chamber, comprises a portion passing through the heating region, and is configured to be occluded upon deformation of the elastomeric layer, to transfer a waste fluid to the waste chamber, and to pass through the vent region.