B81C99/0095

METHOD FOR MANUFACTURING CORE-SHELL NANOWIRE AND NANOWIRE MANUFACTURED THEREBY
20230050510 · 2023-02-16 ·

Provided is a method of fabricating a core-shell structured nanowire on a tip of an optical fiber, on a substrate, or any position on other target objects, and a nanowire fabricated by the method. The nanowire fabricated by the method of the present invention may be used for a drug delivery system, a sensor, an optical waveguide, and the like.

Method for producing a molded body

The present invention relates to a method for producing a molded body (10), comprising the following steps: a) providing a molding tool (40) which has at least one receptacle (12) in which at least one material (30) which comprises at least one shape-memory material (31) is introduced, wherein the shape-memory material (31) is present in a first state (111), wherein the material (30) at least partially fills the receptacle (12) of the molding tool (40) in such a manner that said material adjoins at least one surface of the receptacle (12); b) creating a molded body (10) in the receptacle (12) of the molding tool (40) from the material (30), wherein the shape-memory material (31) is present in a second state (112), wherein a form (11) is embossed into the molded body (10) during the second state (112); c) transferring the shape-memory material (31) to a third state (113), wherein the molded body (10) can be deformed during the third state (113) in such a manner that the molded body (10) is demolded from the receptacle (12) of the molding tool (40); and d) at least partially restoring the form (11) of the molded body (10) by transferring the shape-memory material (31) to a fourth state (114), wherein the molded body (10) at least partially resumes the form (11) according to step b) during the fourth state (114).

3D printing of gel networks

The invention provides a process for producing a gel network, which gel network comprises a plurality of joined gel objects, which process comprises: forming a plurality of gel objects in one or more microfluidic channels; dispensing the gel objects from the one or more microfluidic channels into a region for producing the network; and contacting each gel object with at least one other gel object in said region to join each gel object to at least one other gel object at a region of contact between the gel objects. The invention also provides a network of joined gel objects, comprising a plurality of gel objects, wherein each gel object is joined to an adjacent gel object at a region of contact between the gel objects. Also provided are various possible uses of the gel network.

METHOD FOR PRODUCING A ROLLED-UP ELECTRICAL OR ELECTRONIC COMPONENT

The present invention relates to the fields of physics, material sciences and micro and nano electronics, and concerns a method for producing a rolled-up electrical or electronic component, as can be used for example as a capacitor, or in aerials. The object of the present invention is to provide a low-cost, environmentally friendly and time-saving method for producing a rolled-up electrical or electronic component with many windings. The object is achieved by a method for producing a rolled-up component in which at least two functional and insulating layers, alternately arranged fully or partially over one another, are applied to a substrate with a sacrificial layer, wherein at least the functional or insulating layer that is arranged directly on the sacrificial layer has a perforation, at least on the two sides that are arranged substantially parallel to the rolling direction.

Flow lithography technique to form microstructures using optical arrays

A continuous flow projection lithography system to form microstructures using an optical array incorporated in a continuous coating process is provided. A mask is placed at a distance from the array. Each element of the array projects one image of the mask onto a substrate, effectively forming an array thereon. A coating process allows flows that can be used to define functional regions of particles or supporting layers that prevent adhesion of crosslinked polymers to surfaces.

Pop-Up Laminate Structures with Integrated Electronics

A multi-layer, super-planar laminate structure can be formed from distinctly patterned layers. The layers in the structure can include at least one rigid layer and at least one flexible layer; the rigid layer includes a plurality of rigid segments, and the flexible layer can extend between the rigid segments to serve as a joint. The layers are then stacked and bonded at selected locations to form a laminate structure with inter-layer bonds, and the laminate structure is flexed at the flexible layer between rigid segments to produce an expanded three-dimensional structure, wherein the layers are joined at the selected bonding locations and separated at other locations. A layer with electrical wiring can be included in the structure for delivering electric current to devices on or in the laminate structure.

Semiconductor ICF Target Processing
20210358644 · 2021-11-18 · ·

A method of manufacturing a semiconductor ICF target is described. On an n-type silicon wafer a plurality of hard mask layers are etched to a desired via pattern. Then isotropically etching hemispherical cavities, lithographically patterning the hard mask layers, conformally depositing ablator/drive material(s) and shell layer material(s), inserting hollow silicon dioxide fuel spheres in the hemisphere cavities, thermally bonding a mating wafer with matching hemisphere cavities and etching in ethylene diamine-pryrocatechol-water mixture to selectively remove n-type silicon and liberate the spherical targets.

Pop-up laminate structures with integrated electronics

A multi-layer, super-planar laminate structure can be formed from distinctly patterned layers. The layers in the structure can include at least one rigid layer and at least one flexible layer; the rigid layer includes a plurality of rigid segments, and the flexible layer can extend between the rigid segments to serve as a joint. The layers are then stacked and bonded at selected locations to form a laminate structure with inter-layer bonds, and the laminate structure is flexed at the flexible layer between rigid segments to produce an expanded three-dimensional structure, wherein the layers are joined at the selected bonding locations and separated at other locations. A layer with electrical wiring can be included in the structure for delivering electric current to devices on or in the laminate structure.

Semiconductor ICF target processing
11443937 · 2022-09-13 · ·

A method of manufacturing a semiconductor ICF target is described. On an n-type silicon wafer a plurality of hard mask layers are etched to a desired via pattern. Then isotropically etching hemispherical cavities, lithographically patterning the hard mask layers, conformally depositing ablator/drive material(s) and shell layer material(s), inserting hollow silicon dioxide fuel spheres in the hemisphere cavities, thermally bonding a mating wafer with matching hemisphere cavities and etching in ethylene diamine-pryrocatechol-water mixture to selectively remove n-type silicon and liberate the spherical targets.

METHOD FOR FABRICATING MICRO- OR NANOWIRE AT PREDETERMINED POSITION OF OBJECT USING MICRO- OR NANOPIPETTE
20220242726 · 2022-08-04 ·

Provided is a method of fabricating a micro/nanowire having a nanometer- to micrometer-sized diameter at predetermined positions on an object. The method comprises: preparing a micro/nanopipette having a tip with an inner diameter (d.sub.pt) which is substantially the same as the diameter of the micro/nanowire to be fabricated; filling the micro/nanopipette with a solution containing a micro/nanowire-forming material; bringing the solution into contact with the object through the tip of the micro/nanopipette; and pulling the micro/nanopipette apart from the object at a pulling speed lower than or equal to a predetermined critical pulling speed (v.sub.c) to fabricate a micro/nanowire having substantially the same diameter as the inner diameter of the micro/nanopipette tip (d.sub.pt). The critical pulling speed (v.sub.c) is defined by a maximum limit of the pulling speed at which the micro/nanowire to be fabricated has the same diameter as the inner diameter of the micro/nanopipette tip (d.sub.pt).