Patent classifications
C23C14/5853
CHEMICAL BONDING METHOD, PACKAGE-TYPE ELECTRONIC COMPONENT, AND HYBRID BONDING METHOD FOR ELECTRONIC DEVICE
Substrates that are bonding targets are bonded in ambient atmosphere via bonding films, including oxides, formed on bonding faces of the substrates. The bonding films, which are metal or semiconductor thin films formed by vacuum film deposition and at least the surfaces of which are oxidized, are formed into the respective smooth faces of two substrates having the smooth faces that serve as the bonding faces. The bonding films are exposed to a space that contains moisture, and the two substrates are overlapped in the ambient atmosphere such that the surfaces of the bonding films are made to be hydrophilic and the surfaces of the bonding films contact one another. Through this, a chemical bond is generated at the bonded interface, and thereby the two substrates are bonded together in the ambient atmosphere. The bonding strength γ can be improved by heating the bonded substrates at a temperature.
Black plated steel sheet and manufacturing method thereof
A black plated steel sheet includes a steel sheet and an Al—Mg—Si-based plating layer disposed on one surface or both surfaces of the steel sheet; in which the plating layer includes a black layer on the outermost surface thereof, and the black layer has a weight ratio of O to (Al+Mg+Si+O) of 0.01 to 0.6.
Innovation In High Performance Electro-Chromic Device Manufacturing Method
The invention relates to the manufacturing method of high performance electro-chromic devices containing transition metal oxide based compounds, wherein it comprises the steps of enlarging of the metal contact with Pt (Platinum) (1) sputtering method on one edge of the 80-150 nm thick Indium-Tin oxide alloy (ITO) (2), which was previously enlarged on the glass (3) by the sputter method, growing vertical nano-wall structures at 15-25 mTorr, 300-500° C. substrate temperature and at 3-45 minutes intervals on glass (3) with sputter method, by using transition metal chalcogen targets on previously enlarged ITO (2) with a thickness of 80-150 nm, oxidizing the grown structures in the oxidizing furnace for 10-60 minutes under oxygen gas in the temperature range 300-450° C., preparing the electro-chromic device by placing a counter glass/ITO (80-150 nm) in propylene carbonate (PC) to face 1 Mole/Liter Lithium perchlorate (LiClO4) ion-conducting electrolyte (6) with a 0.5-1 mm distance between them and closing it.
METHOD FOR CREATING PATTERNS
The invention relates in particular to a method for creating patterns in a layer (410) to be etched, starting from a stack comprising at least the layer (410) to be etched and a masking, layer (420) on top of the layer (410) to be etched, the masking layer (420) having at least one pattern (421), the method comprising at least; a) a step of modifying at least one zone (411) of the layer (410) to be etched via ion implantation (430) vertically in line with said at least one pattern (421); b) at least one sequence of steps comprising: b1) a step of enlarging (440) the at least one pattern (421) in a plane in which the layer (410) to be etched mainly extends; b2) a step of modifying at least one zone (411″, 411″) of the layer (410) to be etched via ion implantation (430) vertically in line with the at least one enlarged pattern (421), the implantation being carried out over a depth less than the implantation depth of the preceding, modification step;) c) a step of removing (461, 462) the modified zones (411, 411′, 41″), the removal comprising a step of etching the modified zones (411, 411′, 411″) selectively with respect to the non-modified zones (412) of the layer (410) to be etched.
YTTRIUM INGOT AND SPUTTERING TARGET IN WHICH THE YTTRIUM INGOT IS USED
Provided is an yttrium ingot from which an yttrium sputtering target that produces a reduced number of particles can be obtained, and an yttrium sputtering target that has high plasma resistance and a low resistance that enables realization of a high film deposition rate can be obtained.
An yttrium ingot, wherein the yttrium ingot has a fluorine atom content of less than or equal to 10 wt %; in an instance where the yttrium ingot constitutes a target, a sputtering surface of the target has a surface roughness of 10 nm or greater and 2 μm or less; in the yttrium ingot, the number of pores having a diameter of greater than or equal to 100 μm is fewer than or equal to 0.1/cm.sup.2; and the yttrium ingot has a relative density of greater than or equal to 96%.
Immersion cooling with water-based fluid using nano-structured coating
A method includes coating, via chemical vapor deposition, electronics disposed on a printed circuit board (PCB) with an electrical insulation coating of between one micron to 25 microns. The method further include depositing, on the electrical insulation coating, a metallic nano-layer comprising a porous metallic nano-structure. The method further includes, after the coating and the depositing, immersing the PCB in a water-based fluid to cool the electronics while the electronics are powered on.
ALUMINUM THIN FILM MICROARRAY CHIP SUBSTRATES FOR BIOSENSING VIA SURFACE PLASMON RESONANCE SPECTROSCOPY AND IMAGING
A thin aluminum film substrate and microarrays thereof including a substrate and a thin film of aluminum deposited on the substrate for surface plasmon resonance analysis. Methods of forming the thin aluminum film substrate and microarrays including providing a substrate, using electron-beam physical vapor deposition (EBPVD) to deposit a thin film of Al on a surface of the substrate. Also disclosed are methods of detecting an analyte, wherein a functionalized surface of the thin aluminum film includes a biomolecule and the methods include applying a sample including the analyte to the thin aluminum film substrate, and using surface plasmon resonance (SPR) spectroscopy to detect molecular interactions between the biomolecule and the analyte at a surface of the thin aluminum film substrate. In some examples, an unmodified Al film with an Al.sub.2O.sub.3 layer is effective in enriching phosphorylated peptides. In some examples, a coating of an ionic polymer is used to analyze charged-based interactions of biomolecules.
FABRICATION OF LOW DEFECTIVITY ELECTROCHROMIC DEVICES
Prior electrochromic devices frequently suffer from high levels of defectivity. The defects may be manifest as pin holes or spots where the electrochromic transition is impaired. This is unacceptable for many applications such as electrochromic architectural glass. Improved electrochromic devices with low defectivity can be fabricated by depositing certain layered components of the electrochromic device in a single integrated deposition system. While these layers are being deposited and/or treated on a substrate, for example a glass window, the substrate never leaves a controlled ambient environment, for example a low pressure controlled atmosphere having very low levels of particles. These layers may be deposited using physical vapor deposition. In certain embodiments, the device includes a counter electrode having an anodically coloring electrochromic material in combination with an additive.
Plasma processing device member and plasma processing device provided with same
A plasma processing device member according to the disclosure includes a base material and a film formed of a rare-earth element oxide, or a rare-earth element fluoride, or a rare-earth element oxyfluoride, or a rare-earth element nitride, the film being disposed on at least part of the base material. The film includes a surface to be exposed to plasma, the surface having an arithmetic mean roughness Ra of 0.01 μm or more and 0.1 μm or less, the surface being provided with a plurality of pores, and a value obtained by subtracting an average equivalent circle diameter of the pores from an average distance between centroids of adjacent pores is 28 μm or more and 48 μm or less. A plasma processing device according to the disclosure includes the plasma processing device member described above.
Reducing junction resistance variation in two-step deposition processes
A method of reducing junction resistance variation for junctions in quantum information processing devices fabricated using two-step deposition processes. In one aspect, a method includes providing a dielectric substrate (208), forming a first resist layer (210) on the dielectric substrate, forming a second resist layer (212) on the first resist layer, and forming a third resist layer (214) on the second resist layer. The first resist layer includes a first opening (216) extending through a thickness of the first resist layer, the second resist layer includes a second opening (218) aligned over the first opening and extending through a thickness of the second resist layer, and the third resist layer includes a third opening (220) aligned over the second opening and extending through a thickness of the third resist layer.