Patent classifications
C23C16/06
FORMING LINED COOLING APERTURE(S) IN A TURBINE ENGINE COMPONENT
A manufacturing method is provided. During this method, a preform component is provided for a turbine engine. The preform component includes a substrate. A meter section of a cooling aperture is formed in the substrate. An internal coating is applied onto a surface of the meter section. An external coating is applied over the substrate. A diffuser section of the cooling aperture is formed in the external coating and the substrate to provide the cooling aperture.
FORMING LINED COOLING APERTURE(S) IN A TURBINE ENGINE COMPONENT
A manufacturing method is provided. During this method, a preform component is provided for a turbine engine. The preform component includes a substrate. A meter section of a cooling aperture is formed in the substrate. An internal coating is applied onto a surface of the meter section. An external coating is applied over the substrate. A diffuser section of the cooling aperture is formed in the external coating and the substrate to provide the cooling aperture.
Sensors, methods of making and devices
Disclosed sensors can include at least one resonator (in some embodiments, at least two resonators) and various other structures that may be formed in association with the resonators. The at least one resonator in embodiments can include a bottom electrode, a piezoelectric layer, and a top electrode, wherein the piezoelectric layer is positioned between the bottom electrode and the top electrode.
Sensors, methods of making and devices
Disclosed sensors can include at least one resonator (in some embodiments, at least two resonators) and various other structures that may be formed in association with the resonators. The at least one resonator in embodiments can include a bottom electrode, a piezoelectric layer, and a top electrode, wherein the piezoelectric layer is positioned between the bottom electrode and the top electrode.
FILM FORMING METHOD, FILM FORMING DEVICE, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
A film forming method includes: providing the substrate into the processing container; forming a metal-based film on the substrate within the processing container; and subsequently, supplying a Si-containing gas into the processing container in a state in which the substrate is provided within the processing container.
FILM FORMING METHOD, FILM FORMING DEVICE, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
A film forming method includes: providing the substrate into the processing container; forming a metal-based film on the substrate within the processing container; and subsequently, supplying a Si-containing gas into the processing container in a state in which the substrate is provided within the processing container.
SEMICONDUCTOR PROCESSING CHUCKS FEATURING RECESSED REGIONS NEAR OUTER PERIMETER OF WAFER FOR MITIGATION OF EDGE/CENTER NONUNIFORMITY
Chucks for supporting semiconductor wafers during certain processing operations are disclosed. The chucks may include a recessed region near the outer perimeter of the wafer that has one or more surfaces that face towards the wafer but are recessed therefrom so as to not contact the wafer around the perimeter of the wafer. The use of such a recessed region prevents direct thermally conductive contact between the chuck and the wafer, thereby allowing the wafer to achieve a more uniform temperature distribution in certain process conditions. This has the further effect of causing certain processing operations to be more uniform with respect to edge-center deposition (or etch) layer thickness.
SEMICONDUCTOR PROCESSING CHUCKS FEATURING RECESSED REGIONS NEAR OUTER PERIMETER OF WAFER FOR MITIGATION OF EDGE/CENTER NONUNIFORMITY
Chucks for supporting semiconductor wafers during certain processing operations are disclosed. The chucks may include a recessed region near the outer perimeter of the wafer that has one or more surfaces that face towards the wafer but are recessed therefrom so as to not contact the wafer around the perimeter of the wafer. The use of such a recessed region prevents direct thermally conductive contact between the chuck and the wafer, thereby allowing the wafer to achieve a more uniform temperature distribution in certain process conditions. This has the further effect of causing certain processing operations to be more uniform with respect to edge-center deposition (or etch) layer thickness.
TUNGSTEN FEATURE FILL WITH NUCLEATION INHIBITION
Described herein are methods of filling features with tungsten, and related systems and apparatus, involving inhibition of tungsten nucleation. In some embodiments, the methods involve selective inhibition along a feature profile. Methods of selectively inhibiting tungsten nucleation can include exposing the feature to a direct or remote plasma. In certain embodiments, the substrate can be biased during selective inhibition. Process parameters including bias power, exposure time, plasma power, process pressure and plasma chemistry can be used to tune the inhibition profile. The methods described herein can be used to fill vertical features, such as in tungsten vias, and horizontal features, such as vertical NAND (VNAND) wordlines. The methods may be used for both conformal fill and bottom-up/inside-out fill. Examples of applications include logic and memory contact fill, DRAM buried wordline fill, vertically integrated memory gate/wordline fill, and 3-D integration using through-silicon vias.
TUNGSTEN FEATURE FILL WITH NUCLEATION INHIBITION
Described herein are methods of filling features with tungsten, and related systems and apparatus, involving inhibition of tungsten nucleation. In some embodiments, the methods involve selective inhibition along a feature profile. Methods of selectively inhibiting tungsten nucleation can include exposing the feature to a direct or remote plasma. In certain embodiments, the substrate can be biased during selective inhibition. Process parameters including bias power, exposure time, plasma power, process pressure and plasma chemistry can be used to tune the inhibition profile. The methods described herein can be used to fill vertical features, such as in tungsten vias, and horizontal features, such as vertical NAND (VNAND) wordlines. The methods may be used for both conformal fill and bottom-up/inside-out fill. Examples of applications include logic and memory contact fill, DRAM buried wordline fill, vertically integrated memory gate/wordline fill, and 3-D integration using through-silicon vias.