C23C18/1803

ELECTRONIC DEVICE HOUSINGS WITH ELECTROLESS PLATING LAYERS

In one example, an electronic device housing may include a substrate, a micro-arc oxidation layer formed on a surface of the substrate, and an electroless plating layer formed on the micro-arc oxidation layer. Example electroless plating layer may be one of an electroless tin plating layer and an electroless silver plating layer. Further, the electronic device housing may include an electrophoretic deposition layer formed on the electroless plating layer.

PLATING BATH SOLUTIONS

Compositions for electroless plating baths and their use are disclosed, and more particularly different solutions each usable to both makeup an original bath and to replenishment of the original bath.

ELECTROLESS GOLD PLATING BATH

The electroless gold plating bath includes a gold sulfate, a thiosulfate, ascorbic acid compounds, and hydrazine compounds, the hydrazine compounds being at least one selected from the group consisting of adipic dihydrazide, propionic hydrazide, hydrazine sulfate, hydrazine monohydrochloride, hydrazine dihydrochloride, hydrazine carbonate, hydrazine monohydrate, sebacic dihydrazide, dodecanediohydrazide, isophthalic dihydrazide, hydrazide, 3-hydro-2-naphtboic hydrazide benzophenone hydrazone, phenylhydrazine, benzylhydrazine monohydrochloride, methylhydrazine sulfate, and isopropylhydrazine hydrochloride.

METHOD FOR PRODUCING METAL-PLATED STAINLESS MATERIAL
20170327953 · 2017-11-16 ·

There is provided a method for producing a metal-plated stainless material, the method including performing an acid treatment of treating a stainless steel material with an acidic solution; performing an etching of treating the stainless steel material after the acid treatment with an etching treatment agent; and a modifying the surface of the stainless steel material after the etching into a state suitable for a metal plating process.

Composite member

A composite member includes: a substrate formed of a composite material containing a plurality of diamond grains and a metal phase; and a coating layer made of metal. The surface of the substrate includes a surface of the metal phase, and a protrusion formed of a part of at least one diamond grain of the diamond grains and protruding from the surface of the metal phase. In a plan view, the coating layer includes a metal coating portion, and a grain coating portion. A ratio of a thickness of the grain coating portion to a thickness of the metal coating portion is equal to or less than 0.80. The coating layer has a surface roughness as an arithmetic mean roughness Ra of less than 2.0 μm.

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME

Provided is a semiconductor device, including: a front-back conduction-type semiconductor element; a front-side electrode formed on the front-back conduction-type semiconductor element; an electroless nickel-containing plating layer formed on the front-side electrode; and an electroless gold plating layer formed on the electroless nickel-containing plating layer, wherein the semiconductor device has a low-nickel concentration layer on a side of the electroless nickel-containing plating layer in contact with the electroless gold plating layer, and wherein the low-nickel concentration layer has a thickness smaller than that of the electroless gold plating layer.

Magnetic disc, aluminum alloy substrate for magnetic disc, and production method for aluminum alloy substrate

Provided are a magnetic disk and a method of fabricating the magnetic disk. The magnetic disk includes an aluminum alloy plate fabricated by a process involving a CC method and a compound removal process, and an electroless Ni—P plating layer disposed on the surface of the plate. The aluminum alloy plate is composed of an aluminum alloy containing 0.4 to 3.0 mass % (hereinafter abbreviated simply as “%”) of Fe, 0.1% to 3.0% of Mn, 0.005% to 1.000% of Cu, 0.005% to 1.000% of Zn, with a balance of Al and unavoidable impurities. In the magnetic disk, the maximum amplitude of waviness in a wavelength range of 0.4 to 5.0 mm is 5 nm or less, and the maximum amplitude of waviness in a wavelength range of 0.08 to 0.45 mm is 1.5 nm or less.

METHOD FOR PRODUCING PACKAGE SUBSTRATE FOR LOADING SEMICONDUCTOR DEVICE

A method for manufacturing a package substrate including an insulating layer and a wiring conductor, including: forming, on one or both sides of a core resin layer, a substrate including a peelable first metal layer that has a thickness of 1-70 μm, a first insulating resin layer, and a second metal layer; forming a non-through hole reaching a surface of the first metal layer, performing electrolytic and/or electroless copper plating on its inner wall, and connecting the second and first metal layers; arranging a second insulating resin layer and a third metal layer and heating and pressurizing the first substrate to form a substrate; forming a non-through hole reaching a surface of the second metal layer, performing electrolytic and/or electroless copper plating on its inner wall, and connecting the second and third metal layers; peeling a third substrate; and patterning the first and third metal layers to form the wiring conductor.

Substrate liquid processing apparatus, substrate liquid processing method and recording medium

A substrate processing apparatus includes a substrate holder configured to horizontally hold and rotate a substrate which has a recess and a base metal layer exposed from a bottom surface of the recess; and a pre-cleaning liquid supply configured to supply a pre-cleaning liquid such as dicarboxylic acid or tricarboxylic acid onto the substrate being held and rotated by the substrate holder, to thereby pre-clean the base metal layer. A temperature of the pre-cleaning liquid on the substrate is equal to or higher than 40° C.

Semiconductor device and power conversion device

Even when a stress is applied due to energization or switching operation, a connection state of electrode layers can be appropriately maintained. A semiconductor device includes a semiconductor layer of first conductivity type, an upper surface structure formed on a surface layer of the semiconductor layer, and an upper surface electrode formed over the upper surface structure. The upper surface electrode includes a first electrode formed on an upper surface of the semiconductor layer, and a second electrode formed over an upper surface of the first electrode. The first concave portion is formed on the upper surface of the first electrode. A side surface of the first concave portion has a tapered shape. The second electrode is formed over the upper surface of the first electrode including an inside of the first concave portion.