In a method, an aluminum body is chemically treated with at least one of an alkaline solution and an acid solution. Anode-oxidization is performed on the chemically treated aluminum body to form an aluminum oxide layer. The aluminum oxide layer is treated with hot water at a temperature more than 75° C. or steam. The aluminum oxide layer after being treated with hot water or steam includes plural columnar grains, and an average width of the columnar grains is in a range from 10 nm to 100 nm.

A semi-conductor structure with selective bottom terminal contacting is described. The semiconductor device comprises a first metal layer disposed over a substrate; a conductive layer disposed over the first metal layer; and a second metal layer disposed over the conductive layer, the second metal layer embedding a porous structure comprising a plurality of pores that extend substantially perpendicularly from a top surface of the porous structure toward the conductive layer, wherein only a subset of the plurality of pores open onto the conductive layer.

A method for fabricating calcite channels in a nanofluidic device is described. A porous membrane is attached to a substrate. Calcite is deposited in porous openings in the porous membrane attached to the substrate. A width of openings in the deposited calcite is in a range from 50 to 100 nanometers (nm). The porous membrane is etched to remove the porous membrane from the substrate to form a fabricated calcite channel structure. Each channel has a width in the range from 50 to 100 nm.

Porous solid materials are provided. The porous solid materials include a plurality of interconnected wires forming an ordered network. The porous solid materials may have a predetermined volumetric surface area ranging between 2 m.sup.2/cm.sup.3 and 90 m.sup.2/cm.sup.3, a predetermined porosity ranging between 3% and 90% and an electrical conductivity higher than 100 S/cm. The porous solid materials may have a predetermined volumetric surface area ranging between 3 m.sup.2/cm.sup.3 and 72 m.sup.2/cm.sup.3, a predetermined porosity ranging between 80% and 95% and an electrical conductivity higher than 100 S/cm. The porous solid materials (100) may have a predetermined volumetric surface area ranging between 3 m.sup.2/cm.sup.3 and 85 m.sup.2/cm.sup.3, a predetermined porosity ranging between 65% and 90% and an electrical conductivity higher than 2000 S/cm. Methods for the fabrication of such porous solid materials and devices including such porous solid material are also disclosed.

Disclosed is a technical idea of forming ruthenium and ruthenium-cobalt alloy nanowires having various diameters using electroplating. More particularly, a technology of forming ruthenium and ruthenium-cobalt alloy nanowires on a porous template, on pores of which nanotubes are deposited using atomic layer deposition (ALD), using electroplating, and annealing the ruthenium and ruthenium-cobalt alloy nanowires to form ruthenium-cobalt alloy nanowires having various diameters.

A nanowire array structure having an array of nanopillars located in a well in a material layer. The nanopillars of the array extend in the direction from the well floor towards the well mouth. A hard mask overlies the outer peripheral nanopillars in the array and extends outwards to cover the remainder of the well mouth. An aperture in the hard mask exposes the nanopillars disposed inwardly of the outer peripheral nanopillars. The hard mask planarizes the structure, avoiding formation of large topological features at the periphery of the array of nanopillars, thus facilitating integration of the structure into a semiconductor product. At least some of the outer peripheral nanopillars may be in pores of anodic oxide. There are also disclosed semiconductor products incorporating such nanowire array structures and methods of their fabrication.

At least one embodiment relates to a method for transforming at least part of a valve metal layer into a template that includes a plurality of spaced channels aligned longitudinally along a first direction. The method includes a first anodization step that includes anodizing the valve metal layer in a thickness direction to form a porous layer that includes a plurality of channels. Each channel has channel walls and a channel bottom. The channel bottom is coated with a first insulating metal oxide barrier layer as a result of the first anodization step. The method also includes a protective treatment. Further, the method includes a second anodization step after the protective treatment. The second anodization step substantially removes the first insulating metal oxide barrier layer, induces anodization, and creates a second insulating metal oxide barrier layer. In addition, the method includes an etching step.

An electrical device that includes: a metal barrier layer; an anodic porous oxide region on the metal barrier layer; a trench around the anodic porous oxide region reaching the metal barrier layer; a liner at least on a wall of the trench on a side of the anodic porous oxide region forming an electrical isolation barrier and having an opening onto the anodic porous oxide region; a hard mask arranged above the trenches and the liner having an opening onto the anodic porous oxide region. A corresponding manufacturing method is also disclosed.

In a method, an aluminum body is chemically treated with at least one of an alkaline solution and an acid solution. Anode-oxidization is performed on the chemically treated aluminum body to form an aluminum oxide layer. The aluminum oxide layer is treated with hot water at a temperature more than 75° C. or steam. The aluminum oxide layer after being treated with hot water or steam includes plural columnar grains, and an average width of the columnar grains is in a range from 10 nm to 100 nm.

A cluster of non-collapsed nanowires, a template to produce the same, methods to obtain the template and to obtain the cluster by using the template, and devices having the cluster. The cluster and the template both have an interconnected region and an interconnection-free region.