Patent classifications
C30B11/14
LOW ETCH PIT DENSITY, LOW SLIP LINE DENSITY, AND LOW STRAIN INDIUM PHOSPHIDE
Methods and wafers for low etch pit density, low slip line density, and low strain indium phosphide are disclosed and may include an indium phosphide single crystal wafer having a diameter of 4 inches or greater, having a measured etch pit density of less than 500 cm.sup.−2, and having fewer than 5 dislocations or slip lines as measured by x-ray diffraction imaging. The wafer may have a measured etch pit density of 200 cm.sup.−2 or less, or 100 cm.sup.−2 or less, or 10 cm.sup.−2 or less. The wafer may have a diameter of 6 inches or greater. An area of the wafer with a measured etch pit density of zero may at least 80% of the total area of the surface. An area of the wafer with a measured etch pit density of zero may be at least 90% of the total area of the surface.
LOW ETCH PIT DENSITY, LOW SLIP LINE DENSITY, AND LOW STRAIN INDIUM PHOSPHIDE
Methods and wafers for low etch pit density, low slip line density, and low strain indium phosphide are disclosed and may include an indium phosphide single crystal wafer having a diameter of 4 inches or greater, having a measured etch pit density of less than 500 cm.sup.−2, and having fewer than 5 dislocations or slip lines as measured by x-ray diffraction imaging. The wafer may have a measured etch pit density of 200 cm.sup.−2 or less, or 100 cm.sup.−2 or less, or 10 cm.sup.−2 or less. The wafer may have a diameter of 6 inches or greater. An area of the wafer with a measured etch pit density of zero may at least 80% of the total area of the surface. An area of the wafer with a measured etch pit density of zero may be at least 90% of the total area of the surface.
SUBSTRATE-TRIGGERED DIRECTIONAL SOLIDIFICATION PROCESS FOR SINGLE CRYSTAL SUPERALLOY
The present invention relates to a substrate-triggered single crystal superalloy directional solidification process, including: (1) preparing a single crystal substrate material having crystallographic characteristics that match crystallographic characteristics of the single crystal superalloy; (2) fabricating a single crystal substrate chilling plate using the obtained single crystal substrate material; and (3) applying the obtained single crystal substrate chilling plate in a directional solidification apparatus, and then preparing a single crystal alloy product by performing superalloy melting and directional solidification. Compared with grain selector method and seeding with grain selector method, in addition to control the crystallographic orientation of the single crystal superalloy precisely, the present invention could reduce the height of block and the whole mold through canceling the spiral grain selector, significantly improve the axial heat dissipation and temperature gradient at the solid-liquid interface, and then reduce the occurrence of freckles and stray grains near platform.
SUBSTRATE-TRIGGERED DIRECTIONAL SOLIDIFICATION PROCESS FOR SINGLE CRYSTAL SUPERALLOY
The present invention relates to a substrate-triggered single crystal superalloy directional solidification process, including: (1) preparing a single crystal substrate material having crystallographic characteristics that match crystallographic characteristics of the single crystal superalloy; (2) fabricating a single crystal substrate chilling plate using the obtained single crystal substrate material; and (3) applying the obtained single crystal substrate chilling plate in a directional solidification apparatus, and then preparing a single crystal alloy product by performing superalloy melting and directional solidification. Compared with grain selector method and seeding with grain selector method, in addition to control the crystallographic orientation of the single crystal superalloy precisely, the present invention could reduce the height of block and the whole mold through canceling the spiral grain selector, significantly improve the axial heat dissipation and temperature gradient at the solid-liquid interface, and then reduce the occurrence of freckles and stray grains near platform.
NANOWIRES NETWORK
The present invention refers to a method for preparing a network of nanowires; to a network of nanowires obtainable by said method; to a nonwoven material comprising the network, to an electrode comprising the network, a pharmaceutical composition 10 comprising the network of nanowires, to the use of the network of nanowires and to the use of the nonwoven material.
NANOWIRES NETWORK
The present invention refers to a method for preparing a network of nanowires; to a network of nanowires obtainable by said method; to a nonwoven material comprising the network, to an electrode comprising the network, a pharmaceutical composition 10 comprising the network of nanowires, to the use of the network of nanowires and to the use of the nonwoven material.
SILICON INGOT, SILICON BLOCK, SILICON SUBSTRATE, AND SOLAR CELL
An ingot having a first surface, a second surface opposite to the first surface, and a third surface extending in a first direction from the second surface to the first surface and connecting the first and second surfaces includes a first mono-like crystalline portion, a first intermediate portion including one or more mono-like crystalline sections, and a second mono-like crystalline portion sequentially adjacent to one another in a second direction perpendicular to the first direction. The first and second mono-like crystalline portions have a greater width than the first intermediate portion in the second direction. A first boundary between the first mono-like crystalline portion and the first intermediate portion and a second boundary between the second mono-like crystalline portion and the first intermediate portion each include a coincidence boundary. At least one of the first or second boundary is curved in an imaginary cross section perpendicular to the first direction.
SILICON INGOT, SILICON BLOCK, SILICON SUBSTRATE, AND SOLAR CELL
An ingot having a first surface, a second surface opposite to the first surface, and a third surface extending in a first direction from the second surface to the first surface and connecting the first and second surfaces includes a first mono-like crystalline portion, a first intermediate portion including one or more mono-like crystalline sections, and a second mono-like crystalline portion sequentially adjacent to one another in a second direction perpendicular to the first direction. The first and second mono-like crystalline portions have a greater width than the first intermediate portion in the second direction. A first boundary between the first mono-like crystalline portion and the first intermediate portion and a second boundary between the second mono-like crystalline portion and the first intermediate portion each include a coincidence boundary. At least one of the first or second boundary is curved in an imaginary cross section perpendicular to the first direction.
Low etch pit density, low slip line density, and low strain indium phosphide
Methods and wafers for low etch pit density, low slip line density, and low strain indium phosphide are disclosed and may include an indium phosphide single crystal wafer having a diameter of 4 inches or greater, having a measured etch pit density of less than 500 cm.sup.−2, and having fewer than 5 dislocations or slip lines as measured by x-ray diffraction imaging. The wafer may have a measured etch pit density of 200 cm.sup.−2 or less, or 100 cm.sup.−2 or less, or 10 cm.sup.−2 or less. The wafer may have a diameter of 6 inches or greater. An area of the wafer with a measured etch pit density of zero may at least 80% of the total area of the surface. An area of the wafer with a measured etch pit density of zero may be at least 90% of the total area of the surface.
Low etch pit density, low slip line density, and low strain indium phosphide
Methods and wafers for low etch pit density, low slip line density, and low strain indium phosphide are disclosed and may include an indium phosphide single crystal wafer having a diameter of 4 inches or greater, having a measured etch pit density of less than 500 cm.sup.−2, and having fewer than 5 dislocations or slip lines as measured by x-ray diffraction imaging. The wafer may have a measured etch pit density of 200 cm.sup.−2 or less, or 100 cm.sup.−2 or less, or 10 cm.sup.−2 or less. The wafer may have a diameter of 6 inches or greater. An area of the wafer with a measured etch pit density of zero may at least 80% of the total area of the surface. An area of the wafer with a measured etch pit density of zero may be at least 90% of the total area of the surface.