A semiconductor wafer comprises a substrate wafer of monocrystalline silicon and a dopant-containing epitaxial layer of monocrystalline silicon atop the substrate wafer, wherein a non-uniformity of the thickness of the epitaxial layer is not more than 0.5% and a non-uniformity of the specific electrical resistance of the epitaxial layer is not more than 2%.

A semiconductor wafer comprises a substrate wafer of monocrystalline silicon and a dopant-containing epitaxial layer of monocrystalline silicon atop the substrate wafer, wherein a non-uniformity of the thickness of the epitaxial layer is not more than 0.5% and a non-uniformity of the specific electrical resistance of the epitaxial layer is not more than 2%.

A SiC epitaxial wafer includes a SiC substrate and an epitaxial layer laminated on the SiC substrate, wherein the epitaxial layer contains an impurity element which determines the conductivity type of the epitaxial layer and boron which has a conductivity type different from the conductivity type of the impurity element, and the concentration of boron is less than 1.0×10.sup.14 cm.sup.−3 at any position in the plane of the epitaxial layer.

A semiconductor laminate includes a silicon carbide substrate having a first main surface and a second main surface opposite the first main surface, and an epitaxial layer composed of silicon carbide disposed on the first main surface. The second main surface has an average value of roughness Ra of 0.1 μm or more and 1 μm or less with a standard deviation of 25% or less of the average value.

A semiconductor laminate includes a silicon carbide substrate having a first main surface and a second main surface opposite the first main surface, and an epitaxial layer composed of silicon carbide disposed on the first main surface. The second main surface has an average value of roughness Ra of 0.1 μm or more and 1 μm or less with a standard deviation of 25% or less of the average value.

The present invention provides a growth method of grapheme, which at least comprises the following steps: S1: providing an insulating substrate, placing the insulating substrate in a growth chamber; S2: heating the insulating substrate to a preset temperature, and introducing a gas containing catalytic element into the growth chamber; S3: feeding carbon source into the growth chamber and growing a graphene thin film on the insulating substrate. The present invention adopts a catalytic manner of introducing catalytic element, and rapid grows a high quality graphene on the insulating substrate, which avoids the transition process of the graphene, enables to improve the production yield of the graphene, reduces the growth cost of the graphene, and thus the mass production can be facilitated. The graphene grown by the present invention may be applied in the field of novel graphene electronic devices, graphene transparent conducting film, transparent conducting coating and the like.

A method for manufacturing an epitaxial wafer comprising a silicon carbide substrate and a silicon carbide voltage-blocking-layer, the method includes: epitaxially growing a buffer layer on the substrate, doping a main dopant for determining a conductivity type of the buffer layer and doping an auxiliary dopant for capturing minority carriers in the buffer layer at a doping concentration less than the doping concentration of the main dopant, so that the buffer layer enhances capturing and extinction of the minority carriers, the minority carriers flowing in a direction from the voltage-blocking-layer to the substrate, so that the buffer layer has a lower resistivity than the voltage-blocking-layer, and so that the buffer layer includes silicon carbide as a main component; and epitaxially growing the voltage-blocking-layer on the buffer layer.

A semiconductor wafer of single-crystal silicon has an oxygen concentration per new ASTM of not less than 5.0×10.sup.17 atoms/cm.sup.3 and not more than 6.5×10.sup.17 atoms/cm.sup.3; a nitrogen concentration per new ASTM of not less than 1.0×10.sup.13 atoms/cm.sup.3 and not more than 1.0×10.sup.14 atoms/cm.sup.3; a front side having a silicon epitaxial layer wherein the semiconductor wafer has BMDs whose mean size is not more than 10 nm determined by transmission electron microscopy and whose mean density adjacent to the epitaxial layer is not less than 1.0×10.sup.11 cm.sup.−3, determined by reactive ion etching after having subjected the wafer covered with the epitaxial layer to a heat treatment at a temperature of 780° C. for a period of 3 h and to a heat treatment at a temperature of 600° C. for a period of 10 h.

A semiconductor wafer of single-crystal silicon has an oxygen concentration per new ASTM of not less than 5.0×10.sup.17 atoms/cm.sup.3 and not more than 6.5×10.sup.17 atoms/cm.sup.3; a nitrogen concentration per new ASTM of not less than 1.0×10.sup.13 atoms/cm.sup.3 and not more than 1.0×10.sup.14 atoms/cm.sup.3; a front side having a silicon epitaxial layer wherein the semiconductor wafer has BMDs whose mean size is not more than 10 nm determined by transmission electron microscopy and whose mean density adjacent to the epitaxial layer is not less than 1.0×10.sup.11 cm.sup.−3, determined by reactive ion etching after having subjected the wafer covered with the epitaxial layer to a heat treatment at a temperature of 780° C. for a period of 3 h and to a heat treatment at a temperature of 600° C. for a period of 10 h.

According to the present invention, there is provided a SiC epitaxial wafer including: a 4H-SiC single crystal substrate which has a surface with an off angle with respect to a c-plane as a main surface and a bevel part on a peripheral part; and a SiC epitaxial layer having a film thickness of 20 μm or more, which is formed on the 4H-SiC single crystal substrate, in which a density of an interface dislocation extending from an outer peripheral edge of the SiC epitaxial layer is 10 lines/cm or less.