A device includes a control circuit, a scope circuit, and a time-to-current converter. The control circuit is configured to receive a voltage signal from a voltage-controlled oscillator, delay the voltage signal for a delay time to generate a first control signal, and to generate a second control signal according to the first control signal and the voltage signal. The scope circuit is configured to generate a first current signal in response to the second control signal and the voltage signal. The time-to-current converter is configured generate a second current signal according to the first control signal, the voltage signal, a first switch signal, and a test control signal.

A test and measurement instrument has a user interface configured to allow a user to provide one or more user inputs, a display to display results to the user, a memory, one or more processors configured to execute code to cause the one or more processors to receive a waveform array containing waveforms resulting from sweeping one or more parameters from a set of parameters, recover a clock signal from the waveform array, generate a waveform image for each waveform, render the waveform images into video frames to produce an image array of the video frames, select at least some of the video frames to form a video sequence, and play the video sequence on a display. A method of animating waveform data includes receiving a waveform array containing waveforms resulting from sweeping one or more parameters from a set of parameters, recovering a clock signal from the waveforms, generating a waveform image from each of the waveforms, rendering the waveform images into video frames to produce an image array of the video frames, selecting at least some of the video frames to play as a video sequence, and playing the video sequence on a display.

A composite analog-to-digital converter (ADC) has a low resolution ADC configured to receive and digitize analog data, the low resolution ADC having a low resolution and a high operating speed, one or more high resolution ADCs configured to receive and digitize the analog data, the one or more high resolution ADCs having a resolution higher than the low resolution ADC, and an operating speed lower than the high operating speed of the low resolution ADC, a sample clock generator to provide a sample clock signal to the low resolution ADC and to a clock divider, a mixer to receive the analog data and connected to the one or more high resolution ADCs, a local oscillator connected to the mixer to allow the one or more high resolution ADCs to be tuned to sample a portion of a spectrum of the first ADC. A test and measurement instrument contains a composite ADC. A method of operating a composite analog-to-digital converter (ADC), includes receiving an analog signal at a low resolution ADC that operates at a high speed, receiving the analog signal at one or more high resolution ADCs that operate at a resolution higher than the low resolution ADC and at a lower speed than the operating speed of the low resolution ADC, tuning the high resolution ADC to phase align and time align a signal path for the one or more high resolution ADCs to the signal path for the low resolution ADC, producing a spectrum from the low resolution ADC, and producing a portion of the spectrum from the one or more high resolution ADCs.

A system and method are provided for displaying input signals from a DUT on a display screen. The method includes sending a data stream of digitized data received from the DUT to an FPGA for serial decoding; receiving decoded symbols from the FPGA; identifying valid symbols among the decoded symbols indicating transitions between the decoded symbols; storing the valid symbols with corresponding time-tags as valid packets in memory, and discarding ones of the decoded symbols occurring between the valid symbols; and plotting on the display screen the valid packets occurring between beginning and ending valid packets of the stored valid packets. The beginning valid packet has a corresponding time-tag occurring immediately before a first point time-tag associated with a left edge of the display screen, and the ending valid packet has a corresponding time-tag occurring at or immediately before a last point time-tag associated with a right edge of the display screen.

A test and measurement instrument including a signal generator configured to generate a waveform to be sent over a cable to a device under test (DUT) and a real-time waveform monitor (RTWM) circuit. The RTWM is configured to determine a propagation delay of the cable, capture a first waveform, including an incident waveform and a reflection waveform at a first test point between the signal generator and the DUT, capture a second waveform including at least the incident waveform at a second test point between the signal generator and the DUT, determine a reflection waveform and the incident waveform based on the first waveform and the second waveform, and determine a DUT waveform based on the incident waveform, the reflection waveform, and the propagation delay. The DUT waveform represents the waveform generated by the signal generator as received by the DUT.

The present invention relates to an improved recording of context information for a measurement. For this purpose, it is suggested to receive context information from a user and to generate a dataset comprising the received context information. The context information may comprise one or more voice annotation. By using voice annotations for specifying context information of a measurement, a very simple and easy format for acquiring the context information from a user is achieved.

Methods and apparatus are described for detecting anomalies in a clock signal. Example methods include sensing a clock signal that exhibits alternating phases during normal operation; responsive to sensing the start of a first phase, generating a pulse; and if the pulse terminates before sensing the end of the first phase, asserting a clock stopped detection signal. Example clock anomaly detection apparatus includes a clock signal input for coupling to a clock signal that, during normal operation, oscillates between first and second clock states. An anomaly detection output is asserted if the clock signal remains in the first clock state longer than a first phase expected duration or remains in the second clock state longer than a second phase expected duration.

A test and measurement device includes one or more ports configured to connect to a device under test (DUT), a time domain reflectometry (TDR) source configured receive a source control signal and to produce an incident signal to be applied to the DUT, one or more analog-to-digital converters (ADC) configured to receive a sample clock and sample the incident signal from the TDR source and a time domain reflection (TDR) signal or a time domain transmission (TDT) signal from the DUT to produce an incident waveform and a TDR/TDT waveform, one or more processors configured to execute code to cause the one or more processors to: control a clock synthesizer to produce the sample clock and the source control signal, and use a period of the TDR source, a period of the sample clock, and the number of samples to determine time locations for samples in the incident waveform and the TDR/TDT waveform, and a display configured to display the incident waveform and the TDR/TDT waveform. A method of sampling a waveform using a real-equivalent-time oscilloscope having a time domain reflectometry source, comprising: controlling a clock synthesizer to produce a sample clock and a source control signal; using a time domain reflectometry (TDR) source to receive the source control signal and to produce an incident signal to be applied to a device under test (DUT); receiving the sample clock at one or more analog-to-digital converters (ADC) and sampling the incident signal from the TDR source and a TDR/TDT signal from the DUT to produce an incident waveform and a TDR/TDT waveform; determining time locations for samples in the incident waveform and the TDR/TDT waveform, using a period of the TDR source, a period of the sample clock, and a number of samples; and displaying the incident waveform and the TDR/TDT waveform.

A scheme for noise floor de-embedding by identifying a link or relationship between noise floor from an oscilloscope and phase jitter impact on a toggling signal. The scheme uses phase or electrical spectrum and phase detection for noise floor recognition. The scheme de-embeds the impact from random noise and also removes deterministic noise or jitter from the oscilloscope. The scheme provides accurate jitter analysis for a circuit (e.g., clock data recovery circuit) after de-embedding noise floor for the oscilloscope.

A system maps and stores data in digital three-dimensional oscilloscope, wherein an ADC module has four ADC submodules. Four acquired waveform data are sent to an extraction module, and buffered in a FIFO module. When a trigger signal arrives, FIFO module outputs four extracted waveform data to a mapping address calculation module for calculating a mapping address and a RAM serial number for each point data, and the waveform data comparison and control module performs the reading and writing control of the 4×N dual port RAMs. When mapping number reaches a frame number, the RAM array module outputs its waveform probability values to the upper computer module to convert each value into RBG values, and the display module displays the waveforms of input signals of four channels on a screen according the RBG values.