G01R19/02

METHOD FOR CONTROLLING A CELL CURRENT LIMITING VALUE FOR A BATTERY MANAGEMENT SYSTEM, BATTERY MANAGEMENT SYSTEM

A method for controlling a cell current limiting value for a battery management system. In some examples, the method includes determining quadratic reference currents of a battery cell; calculating a corresponding reference time constant for each reference current using a model for the calculation of a RMS value of a cell current by reference to a continuous current; constituting a diagram for the relationship between the reference time constant and the quadratic reference current; determining a predictive time constant by the comparison of a quadratic measured value of a cell current with the quadratic reference currents; calculating a predictive RMS limiting value of the cell current; calculating a first predictive limiting value for a short predictive time, a second predictive limiting value for a long predictive time, and a third predictive limiting value for a continuous predictive time; and calculating additional RMS limiting value for the cell current.

METHOD FOR CONTROLLING A CELL CURRENT LIMITING VALUE FOR A BATTERY MANAGEMENT SYSTEM, BATTERY MANAGEMENT SYSTEM

A method for controlling a cell current limiting value for a battery management system. In some examples, the method includes determining quadratic reference currents of a battery cell; calculating a corresponding reference time constant for each reference current using a model for the calculation of a RMS value of a cell current by reference to a continuous current; constituting a diagram for the relationship between the reference time constant and the quadratic reference current; determining a predictive time constant by the comparison of a quadratic measured value of a cell current with the quadratic reference currents; calculating a predictive RMS limiting value of the cell current; calculating a first predictive limiting value for a short predictive time, a second predictive limiting value for a long predictive time, and a third predictive limiting value for a continuous predictive time; and calculating additional RMS limiting value for the cell current.

MAGNETIC SENSOR ARRAY PROCESSING FOR INTERFERENCE REDUCTION

Current sensing techniques. In an example, a current sensing method includes: generating a first magnetic field measurement; generating a second magnetic field measurement; generating a frequency estimate of a current; calculating a root-mean-square (RMS) value of an estimated amplitude of the current; and generating a temperature estimate of an integrated circuit (IC) configured to perform the method. The method also includes generating a first weighting factor and a second weighting factor based on the frequency estimate, the RMS value, and the temperature estimate, the first weighting factor to control amplification of the first magnetic field measurement and the second weighting factor to control amplification of the second magnetic field measurement.

MAGNETIC SENSOR ARRAY PROCESSING FOR INTERFERENCE REDUCTION

Current sensing techniques. In an example, a current sensing method includes: generating a first magnetic field measurement; generating a second magnetic field measurement; generating a frequency estimate of a current; calculating a root-mean-square (RMS) value of an estimated amplitude of the current; and generating a temperature estimate of an integrated circuit (IC) configured to perform the method. The method also includes generating a first weighting factor and a second weighting factor based on the frequency estimate, the RMS value, and the temperature estimate, the first weighting factor to control amplification of the first magnetic field measurement and the second weighting factor to control amplification of the second magnetic field measurement.

SYSTEMS AND METHODS FOR AUTOMATED DETECTION OF SWITCH CAPACITOR OPERATION

A power distribution monitoring system (100) is provided that can include a number of features. The system can include a plurality of monitoring devices configured to attach to conductor(s) on a power grid distribution network. In some embodiments, a monitoring device is disposed on each conductor of a three-phase network and utilizes a complex platform of software and hardware to detect faults and disturbances that can be analyzed to determine or predict the risk of wildfires.

SYSTEMS AND METHODS FOR AUTOMATED DETECTION OF SWITCH CAPACITOR OPERATION

A power distribution monitoring system (100) is provided that can include a number of features. The system can include a plurality of monitoring devices configured to attach to conductor(s) on a power grid distribution network. In some embodiments, a monitoring device is disposed on each conductor of a three-phase network and utilizes a complex platform of software and hardware to detect faults and disturbances that can be analyzed to determine or predict the risk of wildfires.

METHOD AND SYSTEM FOR DETECTING SELF-CLEARING, SUB-CYCLE FAULTS
20230003784 · 2023-01-05 ·

A method of detecting self-clearing, sub-cycle faults comprises sensing a current condition and a voltage condition at a location along a power cable. The sensed conditions are relayed to an analyzing device, the analyzing device including a current peak detector. The presence of a measured current value is determined. If the measured current value is greater than a current threshold value, a faulted circuit indicator (FCI) analysis is performed to determine the presence or absence of an FCI fault. If an FCI fault is absent, an incipient fault analysis is performed, wherein the RMS current values before and after a threshold event are compared and the voltage total harmonic distortion (THD) before and after the event are compared. If the two current values are within a first predetermined percentage and the THD values differ by a second predetermined percentage, then an incipient fault is reported. If either the two current values are not within the first predetermined percentage or the THD values do not differ by at least the second predetermined percentage,

Arc fault circuit interrupter (AFCI) with arc signature detection
11705712 · 2023-07-18 · ·

In one example, an arc fault circuit interrupter (AFCI) is provided. The AFCI may include a plurality of current arc signature detection blocks configured to output a plurality of corresponding current arc signatures, and a processor. The processor may be configured to receive each of the plurality of current arc signature from each of plurality of current arc signature detection blocks, respectively, and generate a first trigger signal. The processor may be further configured to assess each of the current arc signatures, determine whether an arc fault exists based on the assessment, and generate the first trigger signal if an arc fault is determined to exist. A method for detecting an arc fault is also provided.

Arc fault circuit interrupter (AFCI) with arc signature detection
11705712 · 2023-07-18 · ·

In one example, an arc fault circuit interrupter (AFCI) is provided. The AFCI may include a plurality of current arc signature detection blocks configured to output a plurality of corresponding current arc signatures, and a processor. The processor may be configured to receive each of the plurality of current arc signature from each of plurality of current arc signature detection blocks, respectively, and generate a first trigger signal. The processor may be further configured to assess each of the current arc signatures, determine whether an arc fault exists based on the assessment, and generate the first trigger signal if an arc fault is determined to exist. A method for detecting an arc fault is also provided.

Charge mode control for power factor correction circuit
11705808 · 2023-07-18 · ·

A control circuit for a power factor correction (PFC) circuit, the control circuit includes a multiplier having first, second, and third multiplier inputs and a multiplier output. The control circuit has an adder having first and second inputs and an output. The first input of the adder is coupled to the multiplier output. The control circuit further includes a root mean square (RMS) calculation circuit configured to determine a square of a root mean square of an input sinusoidal voltage. The RMS calculation circuit has an output coupled to the second multiplier input. An input voltage square calculation circuit is configured to determine a square of the input sinusoidal voltage. The input voltage square calculation circuit has an output coupled to the third multiplier input.