The present application discloses an identification circuit for a power-line carrier signal. During signal transmission on a power line, the amplitude change and duration of a voltage signal on the power line are identified and then decoded into corresponding data, so as to reduce dependency on a power supply voltage during signal identification, and prevent the signal identification rate from decreasing as a result of an increase in the transmission distance, thereby reducing requirements for a system power supply.

Some embodiments described herein include an apparatus having a processor communicatively coupled to a memory. The processor is configured to monitor, at a characteristic controller, a first characteristic of an electronic device. The processor is then configured to receive side-channel signature analysis of the electronic device from a signature analyzer. The processor is configured to determine if the first characteristic of the electronic device has changed or will change in a predefined period of time based on the side-channel signature analysis. The processor is then configured to adjust a second characteristic of the electronic device and/or filtering characteristics such that the side-channel signature analysis reflects predefined side-channel behavior.

Some embodiments described herein include an apparatus having a processor communicatively coupled to a memory. The processor is configured to monitor, at a characteristic controller, a first characteristic of an electronic device. The processor is then configured to receive side-channel signature analysis of the electronic device from a signature analyzer. The processor is configured to determine if the first characteristic of the electronic device has changed or will change in a predefined period of time based on the side-channel signature analysis. The processor is then configured to adjust a second characteristic of the electronic device and/or filtering characteristics such that the side-channel signature analysis reflects predefined side-channel behavior.

A method of detecting self-clearing, sub-cycle faults comprises sensing a current condition and a voltage condition at a location along a power cable. The sensed conditions are relayed to an analyzing device, the analyzing device including a current peak detector. The presence of a measured current value is determined. If the measured current value is greater than a current threshold value, a faulted circuit indicator (FCI) analysis is performed to determine the presence or absence of an FCI fault. If an FCI fault is absent, an incipient fault analysis is performed, wherein the RMS current values before and after a threshold event are compared and the voltage total harmonic distortion (THD) before and after the event are compared. If the two current values are within a first predetermined percentage and the THD values differ by a second predetermined percentage, then an incipient fault is reported. If either the two current values are not within the first predetermined percentage or the THD values do not differ by at least the second predetermined percentage,

In one example, an arc fault circuit interrupter (AFCI) is provided. The AFCI may include a plurality of current arc signature detection blocks configured to output a plurality of corresponding current arc signatures, and a processor. The processor may be configured to receive each of the plurality of current arc signature from each of plurality of current arc signature detection blocks, respectively, and generate a first trigger signal. The processor may be further configured to assess each of the current arc signatures, determine whether an arc fault exists based on the assessment, and generate the first trigger signal if an arc fault is determined to exist. A method for detecting an arc fault is also provided.

In one example, an arc fault circuit interrupter (AFCI) is provided. The AFCI may include a plurality of current arc signature detection blocks configured to output a plurality of corresponding current arc signatures, and a processor. The processor may be configured to receive each of the plurality of current arc signature from each of plurality of current arc signature detection blocks, respectively, and generate a first trigger signal. The processor may be further configured to assess each of the current arc signatures, determine whether an arc fault exists based on the assessment, and generate the first trigger signal if an arc fault is determined to exist. A method for detecting an arc fault is also provided.

A peak detector for a power amplifier is provided that includes a threshold voltage detector configured to pulse a detection current in response to an amplified output signal from the amplifier exceeding a peak threshold. A plurality of such peak detectors may be integrated with a corresponding plurality of power amplifiers in a transmitter. Should any peak detector assert an alarm signal or more than a threshold number of alarm signals during a given period, a controller reduces a gain for the plurality of power amplifiers.

A peak detector for a power amplifier is provided that includes a threshold voltage detector configured to pulse a detection current in response to an amplified output signal from the amplifier exceeding a peak threshold. A plurality of such peak detectors may be integrated with a corresponding plurality of power amplifiers in a transmitter. Should any peak detector assert an alarm signal or more than a threshold number of alarm signals during a given period, a controller reduces a gain for the plurality of power amplifiers.

A peak detector includes an asymmetrical latch having a first input and a second input; and a CMOS converter having a first input coupled to a first output of the asymmetrical latch, a second input coupled to a second output of the asymmetrical latch, and an output.

The present disclosure relates to a detection circuit for detecting oscillations of a regulated supply signal. The detection circuit includes a filter circuit to filter the regulated supply signal in order to obtain a filtered supply signal. A peak value detector circuit is designed to detect an extremum of the filtered supply signal. A comparator circuit is designed to compare the detected extreme value with a threshold value and to indicate an understepping or exceedance of the threshold value.